ADV7390/ADV7391/ADV7392/ADV7393
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
1.71
2.97
1.71
2.6
1.8
3.3
1.8
3.3
1.89
3.63
1.89
3.465
V
V
V
V
POWER SUPPLY REJECTION RATIO
0.002
%/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
fCLKIN
Conditions1
SD/ED
Min
Typ
27
54
Max
Unit
MHz
MHz
MHz
ED (at 54 MHz)
HD
74.25
CLKIN High Time, t9
CLKIN Low Time, t10
CLKIN Peak-to-Peak Jitter Tolerance
40
40
% of one clock cycle
% of one clock cycle
ns
2
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Typ
34.6
4.3
Max
Unit
mA
mA
%
V
pF
ns
Full-Drive Output Current
Low Drive Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Capacitance, COUT
Analog Output Delay1
DAC Analog Output Skew
RSET = 510 Ω, RL = 37.5 Ω
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1, DAC 2, DAC 3
33
37
2.0
0
1.4
10
6
1
DAC 1, DAC 2, DAC 3
ns
1 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. 0 | Page 5 of 96
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