ADV7390/ADV7391/ADV7392/ADV7393
CLKIN
t9
t
t12
10
CONTROL
INPUTS
HSYNC
VSYNC
IN SLAVE MODE
Y2
Y0
Y1
Y3
PIXEL PORT
PIXEL PORT
Cb2
Cb0
Cr0
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
Figure 4. SD Input, 16-Bit 4:4:4 RGB (Input Mode 000)
CLKIN
t12
t9
t10
CONTROL
INPUTS
HSYNC
VSYNC
PIXEL PORT
PIXEL PORT
G0
B0
G1
B1
G2
B2
t11
PIXEL PORT
R0
R1
R2
CONTROL
OUTPUTS
t14
t13
Figure 5. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb (Input Mode 001)
CLKIN*
t9
t10
CONTROL
INPUTS
HSYNC
VSYNC
PIXEL PORT
Cb0
t12
Y0
Cr0
Y1
t12
Cb2
Y2
Cr2
t11
t11
t13
CONTROL
OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
HSYNC VSYNC
), Input Mode 010
Figure 6. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (
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Rev. 0 | Page 10 of 96
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