ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL INPUT/OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Conditions
Min
Typ
4
Max
Unit
V
V
μA
pF
V
V
μA
pF
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
2.0
0.8
10
VIN = VDD_IO
ISOURCE = 400 μA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
2.4
0.4
1
4
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
MPU PORT, I2C MODE1
Conditions
Min
Typ
Max
Unit
See Figure 15
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
0
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
0.6
1.3
0.6
0.6
100
300
300
Setup Time (Stop Condition), t8
MPU PORT, SPI MODE1
0.6
See Figure 16
SCLK Frequency
0
10
35
40
MHz
ns
SPI_SS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
Data Access Time after SCLK Falling Edge, t4
Data Setup Time prior to SCLK Rising Edge, t5
Data Hold Time after SCLK Rising Edge, t6
SPI_SS to SCLK Hold Time, t7
SPI_SS to MISO High Impedance, t8
20
50
50
ns
ns
ns
ns
ns
ns
20
0
0
ns
1 Guaranteed by characterization.
Rev. 0 | Page 6 of 96
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