ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
Y2
Y3
Y0
Y1
PIXEL PORT
PIXEL PORT
Cb0 Cr0 Cb2
Cr2
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
/
Figure 12. HD-SDR, 16-Bit 4:2:2 YCrCb (
) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cr0
Y1
Cb0
Y0
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
) Input Timing Diagram
Figure 13. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (
/
Rev. 0 | Page 13 of 96
ADI [ ADI ]
