ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
PIXEL PORT*
Y2
Y3
Y0
Y1
Cb0 Cr0 Cb2
Cr2
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
/
Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb (
) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
Cr0
Y1
Cb0
Y0
PIXEL PORT
a
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
) Input Timing Diagram
Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (
/
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