ADV7170/ADV7171
TTXREQ Rising Edge Control (TC07 to TC04)
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15
TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a maximum
of 15 CLOCK cycles. See Figure 59.
(Subaddress [SR4–SR0] = 12H to 15H)
TTXREQ Falling Edge Control (TC03 to TC00)
These 8-bit-wide registers are used to enable the NTSC
pedestal/PAL teletext on a line-by-line basis in the vertical
blanking interval for both odd and even fields. Figure 48 and
Figure 49 show the four control registers. A Logic Level 1 in any
of the bits of these registers has the effect of turning the pedestal
off on the equivalent line when used in NTSC. A Logic Level 1
in any of the bits of these registers has the effect of turning on
teletext on the equivalent line when used in PAL.
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of
15 CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If Bit TC03 to Bit TC00 are 00Hex
when bits TC07 to TC04 are changed, the falling edge of
TTXREQ tracks that of the rising edge (that is, the time
between the falling and rising edge remains constant).
See Figure 59.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO7
PCO6 PCO5
PCO4 PCO3
PCO2
PCO1
PCO0
FIELD 1/3
FIELD 1/3
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00)
(Address [SR4 to SR0] = 16H)
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4 PCE7
PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
C/W0 BIT DESCRIPTION
FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9
PCE8
CGMS Data Bits (C/W03 to C/W00)
Figure 48. Pedestal Control Registers
These four data bits are the final four bits of the CGMS data
output stream. Note it is CGMS data ONLY in these bit
positions; that is, WSS data does not share this location.
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
FIELD 1/3
FIELD 1/3
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
CGMS CRC Check Control (C/W04)
When this bit is enabled (1), the last six bits of the CGMS data
(that is, the CRC check sequence) are calculated internally by
the ADV7170/ADV7171. If this bit is disabled (0), the CRC
values in the register are output to the CGMS data stream.
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
FIELD 2/4
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9
TXE8
CGMS Odd Field Control (C/W05)
Figure 49. Teletext Control Registers
When this bit is set (1), CGMS is enabled for odd fields. Note
this is valid only in NTSC mode.
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07 TO TC00)
CGMS Even Field Control (C/W06)
(Address [SR4 to SR0] = 19H)
When this bit is set (1), CGMS is enabled for even fields. Note
this is valid only in NTSC mode.
Teletext control register is an 8-bit-wide register. See Figure 50.
WSS Control (C/W07)
When this bit is set (1), wide screen signaling is enabled. Note
this is valid only in PAL mode.
Rev. C | Page 36 of 64
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