ADV7170/ADV7171
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Figure 50. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
WIDE SCREEN
SIGNAL CONTROL
CGMS ODD FIELD
CONTROL
C/W03 – C/W00
C/W07
C/W05
CGMS DATA BITS
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
CGMS EVEN FIELD
CONTROL
CGMS CRC CHECK
CONTROL
C/W06
C/W04
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
Figure 51. CGMS_WSS Register 0
CGMS_WSS REGISTER 2 C/W1 (C/W27 TO C/W20)
(Address [SR4 to SR0] = 18H)
CGMS_WSS REGISTER 1 C/W1 (C/W17 TO C/W10)
(Address [SR4 to SR0] = 17H)
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53
shows the operations under the control of this register.
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52
shows the operations under the control of this register.
C/W2 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W27 to C/W20)
C/W1 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W15 to C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
CGMS DATA BITS (C/W17 TO C/W16)
These bits are CGMS data bits only.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17 – C/W16
CGMS DATA BITS
C/W15 – C/W10
CGMS/WSS DATA BITS
Figure 52. CGMS_WSS Register 1
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27 – C/W20
CGMS/WSS DATA BITS
Figure 53. CGMS_ WSS Register 2
Rev. C | Page 37 of 64
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