ADV7170/ADV7171
Reserved (MR27)
DAC Output (MR33)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC output
configurations is shown in Table 12.
A Logic Level 0 must be written to this bit.
MODE REGISTER 3 MR3 (MR37 TO MR30)
(Address [SR4 to SR0] = 03H)
Chroma Output Select (MR34)
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the
various operations under the control of Mode Register 3.
With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA).
MR3 BIT DESCRIPTION
Revision Code (MR30 to MR31)
Teletext Enable (MR35)
These bits are read-only and indicate the revision of the device.
This bit must be set to 1 to enable teletext data insertion on the
TTX pin.
VBI Open (MR32)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI
data insertion is not available in Slave Mode 0. Also, when both
TTXREQ Bit Mode Control (MR36)
This bit enables switching of the teletext request signal from a
continuous high signal (MR36 = 0) to a bit wise request signal
(MR36 = 1).
BLANK
BLANK
input control and VBI-open are enabled,
input
control has priority; that is, VBI data insertion does not work.
Input Default Color (MR37)
This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logic Level 0 means that
the color corresponding to 00000000 is displayed. A Logic Level 1
forces the output color to black for 00000000 pixel input video data.
Table 12. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
U
U
CVBS
CVBS
CVBS
CVBS
B
B
U
U
DAC C
DAC D
Y
CVBS
Y
CVBS
G
CVBS
Y
Simultaneous Output
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
RGB and composite
RGB and composite
YUV and composite
YUV and composite
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
RGB and C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
C
C
C
R
R
V
V
C
C
C
C
R
R
V
V
CVBS
Y
C
Y
C
G
C
Y
C
RGB and C
YUV and C
YUV and C
Y
CVBS: Composite video baseband signal
Y:
C:
U:
V:
R:
G:
B:
Luminance component signal (for YUV or Y/C mode)
Chrominance signal (for Y/C mode)
Chrominance component signal (for YUV mode)
Chrominance component signal (for YUV mode)
RED Component video (for RGB mode)
GREEN Component video (for RGB mode)
BLUE Component video (for RGB mode)
Each DAC can be powered on or off individually with the following control bits (0 = ON; 1 = OFF):
MR13-DAC C
MR14-DAC D
MR15-DAC B
MR16-DAC A
Rev. C | Page 32 of 64
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