ADV7170/ADV7171
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1μF
0.01μF
L1
(FERRITE BEAD)
5V (V
)
AA
5V
V
5V (V
)
5V (V
)
AA
AA
10μF
33μF
1, 11, 20, 28, 30
CC
GND
0.1μF
0.1μF
V
AA
25
33
COMP
27
DAC D
DAC C
V
REF
75Ω
75Ω
75Ω
75Ω
ADV7170/
ADV7171
38–42,
2–9, 12–14
26
31
32
5V (V
)
P15–P0
S-VIDEO
AA
4kΩ
RESET
DAC B
DAC A
35
15
SCRESET/RTC
HSYNC
100nF
UNUSED
INPUTS
SHOULD BE
GROUNDED
16
17
22
37
FIELD/VSYNC
BLANK
5V (V
)
CC
5V (V
)
5V (V
)
CC
CC
RESET
100kΩ
5kΩ
5kΩ
TTX
TTXREQ
100Ω
100Ω
TTX
23
24
34
SCLOCK
SDATA
MPU BUS
36
44
TTXREQ
CLOCK
100kΩ
R
SET
5V (V
)
AA
ALSB
18
GND
150Ω
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
10kΩ
10, 19, 21,
29, 43
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 54. Recommended Analog Circuit Layout
HSYNC
The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the
pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz
clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the
correct sequence.
D
Q
13.5MHz
D
Q
CLOCK
HSYNC
CK
CK
Figure 55. Circuit to Generate 13.5 MHz
Rev. C | Page 39 of 64
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