ADV7170/ADV7171
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
BLANK INPUT
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02 TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
1
8 BIT
16 BIT
0
0
1
1
0
1
0
1
MODE 0
74ns DELAY
148ns DELAY
222ns DELAY
MODE 1
MODE 2
MODE 3
Figure 43. Timing Register 0
TIMING MODE REGISTER 1 (TR17 TO TR10)
(Address (SR4 to SR0) = 08H)
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
Timing Register 1 is an 8-bit-wide register.
This bit controls whether the ADV7170/ADV7171 is in
Master or Slave Mode.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
Timing Mode Selection (TR02 to TR01)
These bits control the timing mode of the ADV7170/ ADV7171.
These modes are described in more detail in
the Timing and Control section.
TR1 BIT DESCRIPTION
HSYNC Width (TR11 to TR10)
BLANK Control (TR03)
HSYNC
These bits adjust the
HSYNC to FIELD/VSYNC Delay (TR13 to TR12)
HSYNC
pulse width.
BLANK
This bit controls whether the
part is in slave mode.
input is used when the
Luma Delay (TR05 to TR04)
These bits adjust the position of the
VSYNC
output relative to
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
the FIELD/
output.
HSYNC to FIELD Rising Edge Delay (TR15 to TR14)
Pixel Port Control (TR06)
When the ADV7170/ADV7171 are in Timing Mode 1, these
bits adjust the position of the
FIELD output rising edge.
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected, the data will be set up on
Pin P7 to Pin P0.
HSYNC
output relative to the
VSYNC Width (TR15 to TR14)
When the ADV7170/ADV7171 are configured in Timing
VSYNC
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the
internal timing counters. This bit should be toggled after
power-up, reset or changing to a new timing mode.
Mode 2, these bits adjust the
pulse width.
HSYNC
to Pixel Data Adjust (TR17 to TR16)
HSYNC
This enables the
to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master timing mode and
slave timing mode.
Rev. C | Page 34 of 64
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