ADV7170/ADV7171
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
RGB SYNC
OUTPUT SELECT
MR40
SLEEP MODE
CONTROL
PEDESTAL
CONTROL
MR42
MR46
MR44
0
1
DISABLE
ENABLE
0
1
YC OUTPUT
RGB/YUV OUTPUT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
MR47
(0)
VSYNC_3H
ACTIVE VIDEO
RGB/YUV
CONTROL
FILTER CONTROL
MR43
MR45
MR41
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
0
1
RGB OUTPUT
YUV OUTPUT
Figure 42. Mode Register 4
Active Video Filter Control (MR45)
MODE REGISTER 4 MR4 (MR47 TO MR40)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the sync rise and fall
times are always on spec regardless of which luma filter is
selected. This mode is enabled by a Logic Level 1.
(Address (SR4 to SR0) = 04H)
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)
Sleep Mode Control (MR46)
When this bit is set to 1, sleep mode is enabled. With this mode
enabled, power consumption of the ADV7170/ADV7171 is
reduced to typically 200 nA. The I2C registers can be written to
and read from when the ADV7170/ADV7171 are in sleep
mode. If MR46 is set to a 0 when the device is in sleep mode,
the ADV7170/ADV7171 come out of sleep mode and resume
This bit specifies if the part is in composite video mode or
RGB/YUV mode. Note that in RGB/YUV mode the composite
signal is still available.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RESET
normal operation. Also, if the
signal is applied during
sleep mode, the ADV7170/ADV7171 come out of sleep mode
and resume normal operation.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync
information encoded on all RGB outputs.
Reserved (MR47)
A Logic Level 0 should be written to this bit.
_3H (MR43)
VSYNC
TIMING MODE REGISTER 0 (TR07 TO TR00)
(Address [SR4 to SR0] = 07H)
When this bit is enabled (1) in slave mode, it is possible to
VSYNC
drive the
active low input for 2.5 lines in PAL mode and
3 lines in NTSC mode. When this bit is enabled in master
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
VSYNC
mode, the ADV7170/ADV7171 output an active low
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Pedestal Control (MR44)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 are configured in PAL mode.
Rev. C | Page 33 of 64
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