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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

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型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
FIQ  
Table 170. SWICFG MMR Bit Descriptions  
The fast interrupt request (FIQ) is the exception signal to enter  
the FIQ mode of the processor. It is provided to service data  
transfer or communication channel tasks with low latency. The  
FIQ interface is identical to the IRQ interface providing the  
second-level interrupt (highest priority). Four 32-bit registers  
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.  
Bit  
31:3  
2
Description  
Reserved.  
Programmed interrupt (FIQ). Setting/clearing this bit  
corresponds with setting/clearing Bit 1 of FIQSTA  
and FIQSIG.  
1
Programmed interrupt (IRQ). Setting/clearing this bit  
corresponds with setting/clearing Bit 1 of IRQSTA  
and IRQSIG.  
Table 165. FIQSTA Register  
Name  
Address  
Default Value  
Access  
0
Reserved.  
FIQSTA  
0xFFFF0100  
0x00000000  
R
Note that any interrupt signal must be active for at least the  
equivalent of the interrupt latency time, which is detected by  
the interrupt controller and by the user in the IRQSTA/FIQSTA  
register.  
Table 166. FIQSIG Register  
Name  
Address  
Default Value  
0x00XXX0001  
Access  
FIQSIG  
0xFFFF0104  
R
1 X indicates an undefined value.  
TIMERS  
The ADuC7019/20/21/22/24/25/26/27/28/29 have four general-  
purpose timer/counters.  
Table 167. FIQEN Register  
Name  
Address  
Default Value  
Access  
FIQEN  
0xFFFF0108  
0x00000000  
R/W  
Timer0  
Timer1  
Timer2 or wake-up timer  
Timer3 or watchdog timer  
Table 168. FIQCLR Register  
Name  
Address  
Default Value  
Access  
FIQCLR  
0xFFFF010C  
0x00000000  
W
These four timers in their normal mode of operation can be  
either free running or periodic.  
Bit 31 to Bit 1 of FIQSTA are logically ORd to create the FIQ  
signal to the core and to Bit 0 of both the FIQ and IRQ registers  
(FIQ source).  
In free-running mode, the counter decreases from the  
maximum value until zero scale and starts again at the  
minimum value. (It also increases from the minimum value  
until full scale and starts again at the maximum value.)  
The logic for FIQEN and IRQEN does not allow an interrupt  
source to be enabled in both IRQ and FIQ masks. A bit set to 1  
in FIQEN does, as a side effect, clear the same bit in IRQEN.  
Also, a bit set to 1 in IRQEN does, as a side effect, clear the  
same bit in FIQEN. An interrupt source can be disabled in both  
the IRQEN and FIQEN masks.  
In periodic mode, the counter decrements/increments from the  
value in the load register (TxLD MMR) until zero/full scale and  
starts again at the value stored in the load register.  
The timer interval is calculated as follows:  
Note that to clear an already enabled FIQ source, the user must  
set the appropriate bit in the FIQCLR register. Clearing an  
interrupt’s FIQEN bit does not disable the interrupt.  
If the timer is set to count down then  
(
TxLD  
)
×Prescaler  
Programmed Interrupts  
Interval =  
SourceClock  
Because the programmed interrupts are nonmaskable, they are  
controlled by another register, SWICFG, which simultaneously  
writes into the IRQSTA and IRQSIG registers and/or the  
FIQSTA and FIQSIG registers. The 32-bit SWICFG register is  
dedicated to software interrupts(see Table 170). This MMR  
allows the control of a programmed source interrupt.  
If the timer is set to count up, then  
Fs TxLD × Prescaler  
SourceClock  
(
)
Interval =  
The value of a counter can be read at any time by accessing its  
value register (TxVAL). Note that when a timer is being clocked  
from a clock other than core clock, an incorrect value may be  
read (due to an asynchronous clock system). In this configur-  
ation, TxVAL should always be read twice. If the two readings  
are different, it should be read a third time to get the correct  
value.  
Table 169. SWICFG Register  
Name  
Address  
Default Value  
Access  
SWICFG  
0xFFFF0010  
0x00000000  
W
Timers are started by writing in the control register of the  
corresponding timer (TxCON).  
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