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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
PROGRAMMABLE LOGIC ARRAY (PLA)  
Table 146. PLAELMx Registers  
Every ADuC7019/20/21/22/24/25/26/27/28/29 integrates a  
fully programmable logic array (PLA) that consists of two  
independent but interconnected PLA blocks. Each block  
consists of eight PLA elements, giving each part a total of  
16 PLA elements.  
Name  
Address  
Default Value  
Access  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
PLAELM0  
PLAELM1  
PLAELM2  
PLAELM3  
PLAELM4  
PLAELM5  
PLAELM6  
PLAELM7  
PLAELM8  
PLAELM9  
PLAELM10  
PLAELM11  
PLAELM12  
PLAELM13  
PLAELM14  
PLAELM15  
0xFFFF0B00  
0xFFFF0B04  
0xFFFF0B08  
0xFFFF0B0C  
0xFFFF0B10  
0xFFFF0B14  
0xFFFF0B18  
0xFFFF0B1C  
0xFFFF0B20  
0xFFFF0B24  
0xFFFF0B28  
0xFFFF0B2C  
0xFFFF0B30  
0xFFFF0B34  
0xFFFF0B38  
0xFFFF0B3C  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
Each PLA element contains a two-input lookup table that can  
be configured to generate any logic output function based on  
two inputs and a flip-flop. This is represented in Figure 76.  
0
4
A
2
LOOKUP  
TABLE  
B
3
1
Figure 76. PLA Element  
PLAELMx are Element 0 to Element 15 control registers. They  
configure the input and output mux of each element, select the  
function in the lookup table, and bypass/use the flip-flop. See  
Table 147 and Table 152.  
In total, 30 GPIO pins are available on each ADuC7019/20/21/  
22/24/25/26/27/28/29 for the PLA. These include 16 input pins  
and 14 output pins, which msut be configured in the GPxCON  
register as PLA pins before using the PLA. Note that the  
comparator output is also included as one of the 16 input pins.  
Table 147. PLAELMx MMR Bit Descriptions  
The PLA is configured via a set of user MMRs. The output(s) of  
the PLA can be routed to the internal interrupt system, to the  
Bit  
Value Description  
31:11  
10:9  
8:7  
Reserved.  
Mux 0 control (see Table 152).  
Mux 1 control (see Table 152).  
CONVSTART  
signal of the ADC, to an MMR, or to any of the 16  
PLA output pins.  
6
Mux 2 control. Set by user to select the output  
of Mux 0. Cleared by user to select the bit value  
from PLADIN.  
Mux 3 control. Set by user to select the input  
pin of the particular element. Cleared by user to  
select the output of Mux 1.  
The two blocks can be interconnected as follows:  
Output of Element 15 (Block 1) can be fed back to Input 0  
of Mux 0 of Element 0 (Block 0).  
5
Output of Element 7 (Block 0) can be fed back to the Input 0  
of Mux 0 of Element 8 (Block 1).  
4:1  
Lookup table control.  
Table 145. Element Input/Output  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
0.  
NOR.  
PLA Block 0  
PLA Block 1  
Input  
P3.0  
B AND NOT A.  
NOT A.  
A AND NOT B.  
NOT B.  
EXOR.  
NAND.  
AND.  
EXNOR.  
B.  
NOT A OR B.  
A.  
A OR NOT B.  
OR.  
Element Input  
Output  
P1.7  
P0.4  
P0.5  
P0.6  
P0.7  
P2.0  
P2.1  
P2.2  
Element  
Output  
P4.0  
P4.1  
P4.2  
P4.3  
P4.4  
P4.5  
P4.6  
P4.7  
0
1
2
3
4
5
6
7
P1.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
P1.6  
P0.0  
8
9
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
10  
11  
12  
13  
14  
15  
PLA MMRs Interface  
The PLA peripheral interface consists of the 22 MMRs  
described in this section.  
1.  
0
Mux 4 control. Set by user to bypass the flip-  
flop. Cleared by user to select the flip-flop  
(cleared by default).  
Rev. F | Page 80 of 104