Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 180. T1CON MMR Bit Descriptions
Table 182. T1CAP Register
Bit
Value
Description
Name
Address
Default Value
Access
31:18
17
Reserved.
T1CAP
0xFFFF0330
0x00000000
R/W
Event select bit. Set by user to enable time
capture of an event. Cleared by user to
disable time capture of an event.
Event select range, 0 to 31. These events are
as described in Table 160. All events are
offset by two; that is, Event 2 in Table 160
becomes Event 0 for the purposes of
Timer1.
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurs. This event must be
selected in T1CON.
16:12
11:9
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer (count down or count up)
with a programmable prescaler. The source can be the 32 kHz
external crystal, the core clock frequency, or the internal 32 kHz
oscillator. The clock source can be scaled by a factor of 1, 16,
256, or 32,768. The wake-up timer continues to run when the
core clock is disabled.
Clock select.
Core clock (HCLK).
000
001
010
011
External 32.768 kHz crystal.
P1.0 rising edge triggered.
P0.6 rising edge triggered.
Count up. Set by user for Timer1 to count
up. Cleared by user for Timer1 to count
down by default.
The counter can be formatted as plain 32-bit value or as
hours: minutes: seconds: hundredths.
8
32-BIT
LOAD
7
Timer1 enable bit. Set by user to enable
Timer1. Cleared by user to disable Timer1 by
default.
INTERNAL
OSCILLATOR
PRESCALER
/1, 16, 256
OR 32,768
32-BIT
UP/DOWN
COUNTER
EXTERNAL
CRYSTAL
TIMER2 IRQ
6
Timer1 mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
HCLK
TIMER2
VALUE
5:4
Format.
Figure 79. Timer2 Block Diagram
00
01
10
11
Binary.
Reserved.
The Timer2 interface consists of four MMRs: T2LD, T2VAL,
T2CON, and T2CLRI.
Hr: min: sec: hundredths (23 hours to 0 hour).
Hr: min: sec: hundredths (255 hours to 0
hour).
Table 183. T2LD Register
Name
Address
Default Value
Access
3:0
Prescale.
T2LD
0xFFFF0340
0x00000000
R/W
0000
0100
1000
1111
Source Clock/1.
Source Clock/16.
Source Clock/256.
Source Clock/32,768.
T2LD is a 32-bit register load register.
Table 184. T2VAL Register
Name
Address
Default Value
Access
T2VAL
0xFFFF0344
0xFFFFFFFF
R
Table 181. T1CLRI Register
Name
Address
Default Value
Access
T2VAL is a 32-bit read-only register that represents the current
state of the counter.
T1CLRI
0xFFFF032C
0xFF
W
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
Table 185. T2CON Register
Name
Address
Default Value
Access
T2CON
0xFFFF0348
0x0000
R/W
T2CON is the configuration MMR described in Table 186.
Rev. F | Page 87 of 104
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