Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
There are 23 interrupt sources on the ADuC7019/20/21/22/
24/25/26/27/28/29 that are controlled by the interrupt
controller. Most interrupts are generated from the on-chip
peripherals, such as ADC and UART. Four additional interrupt
sources are generated from external interrupt request pins,
IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core only
recognizes interrupts as one of two types: a normal interrupt
request IRQ or a fast interrupt request FIQ. All the interrupts
can be masked separately.
The four 32-bit registers dedicated to IRQ are IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Table 161. IRQSTA Register
Name
Address
Default Value
Access
IRQSTA
0xFFFF0000
0x00000000
R
IRQSTA (read-only register) provides the current-enabled IRQ
source status. When set to 1, that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register (except for Bit 23) represent
the same interrupt source as described in Table 160.
Table 160. IRQ/FIQ MMRs Bit Description
Table 162. IRQSIG Register
Bit
Description
All interrupts OR’ed (FIQ only)
SWI
Name
Address
Default Value
0x00XXX0001
Access
0
1
IRQSIG
0xFFFF0004
R
1 X indicates an undefined value.
2
Timer0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Timer1
IRQSIG reflects the status of the different IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the IRQSIG
is set; otherwise, it is cleared. The IRQSIG bits are cleared when
the interrupt in the particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR. IRQSIG is read only.
Wake-up timer (Timer2)
Watchdog timer (Timer3)
Flash control
ADC channel
PLL lock
I2C0 slave
I2C0 master
I2C1 master
SPI slave
Table 163. IRQEN Register
Name
Address
Default Value
Access
IRQEN
0xFFFF0008
0x00000000
R/W
IRQEN provides the value of the current enable mask. When
each bit is set to 1, the source request is enabled to create an
IRQ exception. When each bit is set to 0, the source request is
disabled or masked, which does not create an IRQ exception.
SPI master
UART
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
Note that to clear an already enabled interrupt source, the user
must set the appropriate bit in the IRQCLR register. Clearing an
interrupt’s IRQEN bit does not disable the interrupt.
PLA IRQ1
Table 164. IRQCLR Register
External IRQ2
External IRQ3
PWM trip (IRQ only)/PWM sync (FIQ only)
Name
Address
Default Value
Access
IRQCLR
0xFFFF000C
0x00000000
W
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
Rev. F | Page 83 of 104
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