ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
16-BIT
LOAD
Table 186. T2CON MMR Bit Descriptions
Bit
Value Description
WATCHDOG
16-BIT
UP/DOWN
COUNTER
31:11
10:9
Reserved.
Clock source.
RESET
PRESCALER
/1, 16 OR 256
32.768kHz
TIMER3 IRQ
00
01
10
11
External crystal.
External crystal.
Internal oscillator.
Core clock (41 MHz/2CD).
TIMER3
VALUE
Figure 80. Timer3 Block Diagram
Watchdog Mode
8
Count up. Set by user for Timer2 to count up.
Cleared by user for Timer2 to count down by
default.
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register to 0.
T3LD is used as the timeout. The maximum timeout can be
512 sec, using the prescaler/256, and full scale in T3LD. Timer3
is clocked by the internal 32 kHz crystal when operating in
watchdog mode. Note that to enter watchdog mode success-
fully, Bit 5 in the T3CON MMR must be set after writing to the
T3LD MMR.
7
6
Timer2 enable bit. Set by user to enable Timer2.
Cleared by user to disable Timer2 by default.
Timer2 mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
Format.
Binary.
5:4
00
01
10
11
Reserved.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
Hr: min: sec: Hundredths (23 hours to 0 hour).
Hr: min: sec: Hundredths (255 hours to 0 hour).
Prescale.
Source Clock/1 by default.
Source Clock/16.
Source Clock/256 expected for Format 2 and
Format 3.
Source Clock/32,768.
3:0
0000
0100
1000
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
1111
Table 187. T2CLRI Register
Name
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
Address
Default Value
Access
T2CLRI
0xFFFF034C
0xFF
W
Table 188. T3LD Register
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
Name
Address
Default Value
Access
T3LD
0xFFFF0360
0x0000
R/W
Timer3 (Watchdog Timer)
T3LD is a 16-bit register load register.
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Table 189. T3VAL Register
Name
Address
Default Value
Access
T3VAL
0xFFFF0364
0xFFFF
R
Normal Mode
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source
is 32 kHz from the PLL and can be scaled by a factor of 1, 16,
or 256 (see Figure 80).
Table 190. T3CON Register
Name
Address
Default Value
Access
T3CON
0xFFFF0368
0x0000
R/W
T3CON is the configuration MMR described in Table 191.
Rev. F | Page 88 of 104
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