ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 153. PLAADC Register
Table 156. PLADIN MMR Bit Descriptions
Name
Address
Default Value
Access
Bit
Description
PLAADC
0xFFFF0B48
0x00000000
R/W
31:16
15:0
Reserved.
Input bit to Element 15 to Element 0.
PLAADC is the PLA source for the ADC start conversion signal.
Table 157. PLADOUT Register
Table 154. PLAADC MMR Bit Descriptions
Name
Address
Default Value
Access
Bit
31:5
4
Value Description
PLADOUT
0xFFFF0B50
0x00000000
R
Reserved.
ADC start conversion enable bit. Set by user
PLADOUT is a data output MMR for PLA. This register is
always updated.
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
Table 158. PLADOUT MMR Bit Descriptions
3:0
ADC start conversion source.
PLA Element 0.
PLA Element 1.
Bit
Description
0000
0001
1111
31:16
15:0
Reserved.
Output bit from Element 15 to Element 0.
PLA Element 15.
Table 159. PLALCK Register
Table 155. PLADIN Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PLALCK
0xFFFF0B54
0x00
W
PLADIN
0xFFFF0B4C
0x00000000
R/W
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
PLADIN is a data input MMR for PLA.
Rev. F | Page 82 of 104
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