Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (TxCLRI).
The Timer0 interface consists of four MMRs: T0LD, T0VAL,
T0CON, and T0CLRI.
Table 172. T0LD Register
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x0000
R/W
When using an asynchronous clock-to-clock timer, the
interrupt in the timer block may take more time to clear
than the time it takes for the code in the interrupt routine to
execute. Ensure that the interrupt signal is cleared before
leaving the interrupt service routine. This can be done by
checking the IRQSTA MMR.
T0LD is a 16-bit load register.
Table 173. T0VAL Register
Name
Address
Default Value
Access
T0VAL
0xFFFF0304
0xFFFF
R
T0VAL is a 16-bit read-only register representing the current
state of the counter.
Hour:Minute:Second:1/128 Format
To use the timer in hour:minute:second:hundredths format,
select the 32,768 kHz clock and prescaler of 256. The hun-
dredths field does not represent milliseconds but 1/128 of
a second (256/32,768). The bits representing the hour,
minute, and second are not consecutive in the register.
This arrangement applies to TxLD and TxVAL when using
the hour:minute:second:hundredths format as set in
TxCON[5:4]. See Table 171 for additional details.
Table 174. T0CON Register
Name
Address
Default Value
Access
T0CON
0xFFFF0308
0x0000
R/W
T0CON is the configuration MMR described in Table 175.
Table 175. T0CON MMR Bit Descriptions
Bit
15:8
7
Value Description
Reserved.
Timer0 enable bit. Set by user to enable Timer0.
Table 171. Hour:Minnute:Second:Hundredths Format
Cleared by user to disable Timer0 by default.
Bit
Value
Description
6
Timer0 mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
Reserved.
Prescale.
Core Clock/1. Default value.
Core Clock/16.
Core Clock/256.
Undefined. Equivalent to 00.
Reserved.
31:24
23:22
21:16
15:14
13.8
7
0 to 23 or 0 to 255
0
0 to 59
0
0 to 59
0
Hours
Reserved
Minutes
Reserved
Seconds
Reserved
1/128 second
5:4
3:2
00
01
10
11
6:0
0 to 127
Timer0 (RTOS Timer)
1:0
Timer0 is a general-purpose, 16-bit timer (count down) with a
programmable prescaler (see Figure 77). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
Table 176. T0CLRI Register
Name
Address
Default Value
Access
T0CLRI
0xFFFF030C
0xFF
W
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt.
Timer0 can be used to start ADC conversions as shown in the
block diagram in Figure 77.
16-BIT
LOAD
16-BIT
PRESCALER
/1, 16 OR 256
TIMER0 IRQ
DOWN
HCLK
COUNTER
ADC CONVERSION
TIMER0
VALUE
Figure 77. Timer0 Block Diagram
Rev. F | Page 85 of 104
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