Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 148. PLACLK Register
Table 150. PLAIRQ Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PLACLK
0xFFFF0B40
0x00
R/W
PLAIRQ
0xFFFF0B44
0x00000000
R/W
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 44 MHz.
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 151. PLAIRQ MMR Bit Descriptions
Table 149. PLACLK MMR Bit Descriptions
Bit
Value
Description
Bit
Value
Description
15:13
12
Reserved.
7
Reserved.
PLA IRQ1 enable bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
6:4
Block 1 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
000
001
010
011
100
101
Other
11:8
PLA IRQ1 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
0000
0001
1111
7:5
4
3
Reserved.
2:0
Block 0 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
000
001
010
011
100
101
Other
3:0
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
0000
0001
1111
Table 152. Feedback Configuration
Bit
Value
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
10:9
00
01
10
11
00
01
10
11
8:7
Rev. F | Page 81 of 104
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