Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 140. I2CxDIV Registers
Table 144. I2C0FSTA MMR Bit Descriptions
Name
Address
Default Value
0x1F1F
Access
R/W
Access
Type
Bit
15:10
9
Value Description
I2C0DIV
I2C1DIV
0xFFFF0830
0xFFFF0930
Reserved.
Master transmit FIFO flush. Set by the
0x1F1F
R/W
R/W
I2CxDIV are the clock divider registers.
user to flush the master Tx FIFO.
Cleared automatically when the
master Tx FIFO is flushed. This bit
also flushes the slave receive FIFO.
Slave transmit FIFO flush. Set by the
user to flush the slave Tx FIFO. Cleared
automatically after the slave Tx FIFO
is flushed.
Master Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Table 141. I2CxIDx Registers
Name
Address
Default Value
0x00
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
0xFFFF0838
0xFFFF083C
0xFFFF0840
0xFFFF0844
0xFFFF0938
0xFFFF093C
0xFFFF0940
0xFFFF0944
8
R/W
R
0x00
0x00
0x00
7:6
0x00
00
01
10
11
0x00
0x00
0x00
5:4
3:2
1:0
R
R
R
Master Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
00
01
10
11
Table 142. I2CxCCNT Registers
Name
Address
Default Value
Access
R/W
I2C0CCNT
I2C1CCNT
0xFFFF0848
0xFFFF0948
0x01
0x01
R/W
00
01
10
11
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
Table 143. I2CxFSTA Registers
Name
Address
Default Value
0x0000
Access
R/W
00
01
10
11
I2C0FSTA
I2C1FSTA
0xFFFF084C
0xFFFF094C
0x0000
R/W
I2CxFSTA are FIFO status registers.
Rev. F | Page 79 of 104
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