ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 137. I2CxALT Registers
Table 138. I2CxCFG Registers
Name
Address
Default Value
0x00
Access
R/W
Name
Address
Default Value
Access
R/W
I2C0ALT
I2C1ALT
0xFFFF0828
0xFFFF0928
I2C0CFG
I2C1CFG
0xFFFF082C
0xFFFF092C
0x00
0x00
0x00
R/W
R/W
I2CxALT are hardware general call ID registers used in slave mode.
I2CxCFG are configuration registers.
Table 139. I2C0CFG MMR Bit Descriptions
Bit
Description
31:5 Reserved. These bits should be written by the user as 0.
14
Enable stop interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start
condition and matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition.
13
12
11
10
9
Reserved.
Reserved.
Enable stretch SCL (holds SCL low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line.
Reserved.
Slave Tx FIFO request interrupt enable. Set by the user to disable the slave Tx FIFO request interrupt. Cleared by the user to generate
an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if
it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate action, taking
interrupt latency into account.
8
7
6
5
4
General call status bit clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general
call status bits are cleared.
Master serial clock enable bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial
clock in master mode.
Loopback enable bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate
in normal mode.
Start backoff disable bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit. Cleared by
user to enable start backoff. After losing arbitration, the master waits before trying to retransmit.
Hardware general call enable. When this bit and Bit 3 are set and have received a general call (Address 0x00) and a data byte, the
device checks the contents of I2C0ALT against the receive register. If the contents match, the device has received a hardware general
call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a
“to whom it may concern” call. The ADuC7019/20/21/22/24/25/26/27/28/29 watch for these addresses. The device that requires
attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and
acts appropriately. The LSB of the I2C0ALT register should always be written to 1, as indicated in The I2C-Bus Specification, January
2000, from NXP.
3
General call enable bit. This bit is set by the user to enable the slave device to acknowledge (ACK) an I2C general call, Address 0x00
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware)
as the data byte, the I2C interface resets as as indicated in The I2C-Bus Specification, January 2000, from NXP. This command can be
used to reset an entire I2C system. The general call interrupt status bit sets on any general call. The user must take corrective action by
setting up the I2C interface after a reset. If it receives a 0x04 (write programmable part of slave address by hardware) as the data byte,
the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address.
2
1
0
Reserved.
Master enable bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel.
Slave enable bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0,
I2C0ID1, I2C0ID2, and I2C0ID3. At 400 kSPs, the core clock should run at 41.78 MHz because the interrupt latency could be up to 45
clock cycles alone. After the I2C read bit, the user has 0.5 of an I2C clock cycle to load the Tx FIFO. AT 400 kSPS, this is 1.26 μs, the
interrupt latency.
Rev. F | Page 78 of 104
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