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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
I2C-COMPATIBLE INTERFACES  
Slave Addresses  
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain  
the device IDs. The device compares the four I2C0IDx registers  
to the address byte. To be correctly addressed, the seven MSBs of  
either ID register must be identical to that of the seven MSBs of  
the first received address byte. The LSB of the ID registers (the  
transfer direction bit) is ignored in the process of address  
recognition.  
The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed  
I2C interfaces. The I2C interfaces are both implemented as a hard-  
ware master and a full slave interface. Because the two I2C inter-  
faces are identical, this data sheet describes only I2C0 in detail.  
Note that the two masters and one of the slaves have individual  
interrupts (see the Interrupt System section).  
Note that when configured as an I2C master device, the  
ADuC7019/20/21/22/24/25/26/27/28/29 cannot generate a  
repeated start condition.  
I2C Registers  
The I2C peripheral interface consists of 18 MMRs, which are  
discussed in this section.  
The two GPIO pins used for data transfer, SDAx and SCLx, are  
configured in a wired-AND format that allows arbitration in a  
multimaster system. These pins require external pull-up resistors.  
Typical pull-up values are 10 kΩ.  
The I2C bus peripheral address in the I2C bus system is pro-  
grammed by the user. This ID can be modified any time a  
transfer is not in progress. The user can configure the interface  
to respond to four slave addresses.  
Table 126. I2CxMSTA Registers  
Name  
Address  
Default Value  
Access  
R/W  
I2C0MSTA  
I2C1MSTA  
0xFFFF0800  
0xFFFF0900  
0x00  
0x00  
R/W  
I2CxMSTA are status registers for the master channel.  
Table 127. I2C0MSTA MMR Bit Descriptions  
The transfer sequence of an I2C system consists of a master  
device initiating a transfer by generating a start condition while  
the bus is idle. The master transmits the slave device address  
and the direction of the data transfer during the initial address  
transfer. If the master does not lose arbitration and the slave  
acknowledges, the data transfer is initiated. This continues until  
the master issues a stop condition and the bus becomes idle.  
The I2C peripheral can be configured only as a master or slave  
at any given time. The same I2C channel cannot simultaneously  
support master and slave modes.  
Access  
Bit Type  
Description  
7
R/W  
Master transmit FIFO flush. Set by user to flush  
the master Tx FIFO. Cleared automatically after  
the master Tx FIFO is flushed. This bit also  
flushes the slave receive FIFO.  
Master busy. Set automatically if the master is  
busy. Cleared automatically.  
Arbitration loss. Set in multimaster mode if  
another master has the bus. Cleared when the  
bus becomes available.  
No ACK. Set automatically if there is no  
acknowledge of the address by the slave  
device. Cleared automatically by reading the  
I2C0MSTA register.  
Master receive IRQ. Set after receiving data.  
Cleared automatically by reading the I2C0MRX  
register.  
Master transmit IRQ. Set at the end of a  
transmission. Cleared automatically by writing  
to the I2C0MTX register.  
Master transmit FIFO underflow. Set  
automatically if the master transmit FIFO is  
underflowing. Cleared automatically by  
writing to the I2C0MTX register.  
Master TX FIFO not full. Set automatically if the  
slave transmit FIFO is not full. Cleared automati-  
cally by writing twice to the I2C0STX register.  
6
5
R
R
4
R
Serial Clock Generation  
The I2C master in the system generates the serial clock for a  
transfer. The master channel can be configured to operate in  
fast mode (400 kHz) or standard mode (100 kHz).  
3
2
1
R
R
R
The bit rate is defined in the I2C0DIV MMR as follows:  
fUCLK  
fSERIAL CLOCK  
=
(2 + DIVH) + (2 + DIVL)  
where:  
UCLK = clock before the clock divider.  
f
DIVH = the high period of the clock.  
DIVL = the low period of the clock.  
0
R
Thus, for 100 kHz operation,  
DIVH = DIVL = 0xCF  
Table 128. I2CxSSTA Registers  
and for 400 kHz,  
Name  
Address  
Default Value  
0x01  
Access  
DIVH = 0x28, DIVL = 0x3C  
The I2CxDIV registers correspond to DIVH:DIVL.  
I2C0SSTA  
I2C1SSTA  
0xFFFF0804  
0xFFFF0904  
R
R
0x01  
I2CxSSTA are status registers for the slave channel.  
Rev. F | Page 76 of 104