ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOSTDP A/C Timing-Host Read Cycle
Table 54 and Figure 45 describe the HOSTDP A/C host read
cycle timing requirements.
Table 54. Host Read Cycle Timing Requirements
Parameter
Min
Max
Units
Timing Requirements
tSADRDL
HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge
4
2.5
ns
ns
ns
ns
ns
tHADRDH HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge
tRDWL
tRDWL
tRDWH
HOST_RD Pulse Width Low (ACK Mode)
HOST_RD Pulse Width Low (INT Mode)
HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and 2 × tSCLK
HOST_WR Falling Edge
tDRDYRDL + tRDYPRD + tDRDHRDY
1.5 × tSCLK + 8.7
tDRDHRDY HOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0
ns
Switching Characteristics
tSDATRDY HOST_D15–0 Valid Prior HOST_ACK Rising Edge (ACK Mode)
tDRDYRDL HOST_ACK Falling Edge After HOST_CE (ACK Mode)
tSCLK – 4.0
ns
ns
ns
ns
ns
ns
11.25
NM1
8.0
tRDYPRD
tDDARWH HOST_D15–0 Disable After HOST_RD
tACC HOST_D15–0 Valid After HOST_RD Falling Edge (INT Mode)
tHDARWH HOST_D15–0 Hold After HOST_RD Rising Edge
HOST_ACK Low Pulse-Width for Read Access (ACK Mode)
1.5 × tSCLK
1.0
1 NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host
DMA FIFO status. This is system design dependent.
HOST_ADDR
HOST_CE
tSADRDL
tHADRDH
tRDWL
tRDWH
HOST_RD
tSDATRDY
tACC
tDDARWH
tHDARWH
HOST_DATA
tDRDHRDY
tDRDYRDL
tRDYPRD
HOST_ACK
In Figure 45, HOST_DATA is HOST_D0–D15.
Figure 45. HOSTDP A/C—Host Read Cycle
Rev. C
|
Page 72 of 100
|
February 2010
ADI [ ADI ]
