ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Up/Down Counter/Rotary Encoder Timing
Table 49 and Figure 42 describe up/down counter/rotary
encoder timing.
Table 49. Up/Down Counter/Rotary Encoder Timing
Parameter
Min
Max
Unit
Timing Requirements
tWCOUNT
tCIS
CUD/CDG/CZM Input Pulse Width
tSCLK + 1
7.2
ns
ns
ns
CUD/CDG/CZM Input Setup Time Before CLKOUT High1
tCIH
CUD/CDG/CZM Input Hold Time After CLKOUT High1
0.0
1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLKOUT
tCIS
tCIH
CUD/CDG/CZM
tWCOUNT
Figure 42. Up/Down Counter/Rotary Encoder Timing
Rev. C
|
Page 68 of 100
|
February 2010
ADI [ ADI ]
