ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Register and PIO
Table 58 and Figure 47 describe the ATAPI register and the PIO
data transfer timing.
Table 58. ATAPI Register and PIO Data Transfer Timing
ATAPI_REG/PIO_TIM_xTimingRegister
Setting1
ATAPI Parameter/Description
Timing Equation
t0
t1
Cycle time
ATAPI_ADDR valid to
ATAPI_DIOR/ATAPI_DIOW setup
T2_PIO, TEOC_PIO
T1
(T2_PIO + TEOC_PIO) × tSCLK
T1 × tSCLK – (tSK1 + tSK2 + tSK4)
t2
t2i
t3
t4
t5
t6
t9
ATAPI_DIOR/ATAPI_DIOW pulse width
ATAPI_DIOR/ATAPI_DIOW recovery time TEOC_PIO
T2_PIO
T2_PIO × tSCLK
TEOC_PIO × tSCLK
T2_PIO × tSCLK – (tSK1 + tSK2 + tSK4
T4 × tSCLK – (tSK1 + tSK2 + tSK4
tOD + tSUD + 2 × tBD + tCDD + tCDC
ATAPI_DIOW data setup
ATAPI_DIOW data hold
ATAPI_DIOR data setup
ATAPI_DIOR data hold
ATAPI_DIOR/ATAPI_DIOW to ATAPI_ADDR TEOC_PIO
valid hold
T2_PIO
T4
N/A
)
)
N/A
0
TEOC_PIO × tSCLK – (tSK1 + tSK2 + tSK4
)
tA
ATAPI_IORDY setup time
T2_PIO
T2_PIO × tSCLK – (tOD + tSUI + 2 × tCDC + 2 × tBD)
1 ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for the ATA device mode of
operation.
Figure 47 displays the REG and PIO data transfer timing. Note
that ATAPI_ADDR pins include A1-3, ATAPI_CS0, and
ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins
include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0,
and ATAPI_CS1. Note that an alternate ATAPI_D0-15 port bus
is ATAPI_D0-15A
t0
ATAPI
ADDR
t9
t1
t2
t2i
ATAPI_DIOR/
ATAPI_DIOW
ATAPI_D0–15
(WRITE)
t3
t4
ATAPI_D0–15
(READ)
tA
t5
t6
ATAPI_IORDY
ATAPI_IORDY
Figure 47. REG and PIO Data Transfer Timing1
1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the
Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.
Rev. C
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Page 75 of 100
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February 2010
ADI [ ADI ]
