ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 51. SD/SDIO Controller Timing (High Speed Mode)
Parameter
Min
Max
Unit
Timing Requirements
tISU
tIH
SD_Dx and SD_CMD Input Setup Time
SD_Dx and SD_CMD Input Hold Time
7.2
2
ns
ns
Switching Characteristics
fPP
tWL
tWH
SD_CLK Frequency During Data Transfer Mode1
SD_CLK Low Time
0
9.5
9.5
40
MHz
ns
ns
SD_CLK High Time
tTLH
tTHL
tODLY
tOH
SD_CLK Rise Time
SD_CLK Fall Time
SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode
SD_Dx and SD_CMD Output Hold Time
3
3
2
ns
ns
ns
ns
2.5
1 tPP=1/fPP
VOH (MIN)
tPP
SD_CLK
INPUT
tTHL
tTLH
tISU
tIH
VOL (MAX)
tWL
tWH
tODLY
tOH
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 44. SD/SDIO Controller Timing (High Speed Mode)
Rev. C
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Page 70 of 100
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February 2010
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