ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Multiword DMA Transfer Timing
Table 59 and Figure 48 through Figure 51 describe the ATAPI
multiword DMA transfer timing.
Table 59. ATAPI Multiword DMA Transfer Timing
ATAPI_MULTI_TIM_x Timing Register
ATAPI Parameter/Description
Setting1
Timing Equation
(TD + TK) × tSCLK
TD × tSCLK
t0
Cycle time
TD, TK
tD
ATAPI_DIOR/ATAPI_DIOW asserted TD
Pulse Width
tF
ATAPI_DIOR data hold
ATAPI_DIOW data setup
ATAPI_DIOR data setup
ATAPI_DIOW data hold
N/A
0
tG(write)
tG(read)
tH
TD
TD
TK
TD × tSCLK – (tSK1 + tSK2 + tSK4)
tOD + tSUD + 2 × tBD + tCDD + tCDC
TK × tSCLK – (tSK1 + tSK2 + tSK4
TM × tSCLK – (tSK1 + tSK2 + tSK4
)
tI
ATAPI_DMACK to
ATAPI_DIOR/ATAPI_DIOW setup
TM
)
tJ
ATAPI_DIOR/ATAPI_DIOW to
ATAPI_DMACK hold
TK, TEOC_MDMA
(TK + TEOC_MDMA) × tSCLK – (tSK1 + tSK2 + tSK4
)
)
tKR
tKW
tLR
tM
ATAPI_DIOR negated pulse width TKR
ATAPI_DIOW negated pulse width TKW
ATAPI_DIOR to ATAPI_DMARQ delay N/A
TKR × tSCLK
TKW × tSCLK
(TD + TK) × tSCLK – (tOD + 2 × tBD + 2 × tCDC
)
ATAPI_CS0-1 valid to
ATAPI_DIOR/ATAPI_DIOW
TM
TM × tSCLK – (tSK1 + tSK2 + tSK4
)
tN
ATAPI_CS0-1 hold
TK, TEOC_MDMA
(TK + TEOC_MDMA) × tSCLK – (tSK1 + tSK2 + tSK4
1 ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for an ATA device mode of
operation.
Rev. C
|
Page 76 of 100
|
February 2010
ADI [ ADI ]
