ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Nonautomotive 400 MHz1
All Other Devices2
Parameter
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
IDD-TYP
VDDINT Current
VDDINT Current
VDDINT Current
VDDINT Current
VDDINT = 1.10 V,
145
178
mA
f
CCLK = 300 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
IDD-TYP
IDD-TYP
IDD-TYP
VDDINT = 1.20 V,
fCCLK = 400 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
199
239
301
360
60
mA
mA
mA
µA
ASF = 1.00
VDDINT = 1.25 V,
fCCLK = 533 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
VDDINT = 1.35 V,
f
CCLK = 600 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
13, 14
IDDHIBERNATE
Hibernate State
Current
VDDEXT = VDDVR = VDDUSB
= 3.30 V,
60
VDDDDR = 2.5 V,
TJ = 25°C,
CLKIN= 0 MHz with
voltage regulator off
(VDDINT = 0 V)
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
VDDUSB = 3.3 V,
20
9
20
9
µA
mA
IDDUSB-FS
VDDUSB Current in
Full/Low Speed Mode TJ = 25°C, Full Speed
USB Transmit
IDDUSB-HS
VDDUSB Current in High VDDUSB = 3.3 V,
25
25
mA
Speed Mode
TJ = 25°C, High Speed
USB Transmit
13, 15
IDDDEEPSLEEP
VDDINT Current in Deep fCCLK = 0 MHz,
Sleep Mode fSCLK = 0 MHz
VDDINIT Current in Sleep fCCLK = 0 MHz,
Table 17
Table 18 mA
13, 15
IDDSLEEP
IDDDEEPSLEEP
IDDDEEPSLEEP mA16
Mode
fSCLK > 0 MHz
+ (0.77 ×
+ (0.77 ×
VDDINT
×
VDDINT ×
16
16
fSCLK
)
fSCLK
)
15, 17
IDDINT
VDDINT Current
fCCLK > 0 MHz,
fSCLK > 0 MHz
IDDSLEEP
(Table 20
× ASF)
+
IDDSLEEP + mA
(Table 20
× ASF)
1 Applies to all nonautomotive 400 MHz speed grade models. See Ordering Guide.
2 Applies to all 533 MHz and 600 MHz speed grade models and automotive 400 MHz speed grade models. See Ordering Guide.
3 Applies to output and bidirectional pins, except USB_VBUS and the pins listed in table note 4.
4 Applies to pins DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE.
5 Applies to all input pins except JTAG inputs.
6 Applies to JTAG input pins (TCK, TDI, TMS, TRST).
7 Applies to DDR_VREF pin.
8 Absolute value.
9 For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = VDDDDR Maximum.
10Applies to three-statable pins.
11For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = 0V.
12Guaranteed, but not tested
Rev. C
|
Page 37 of 100
|
February 2010
ADI [ ADI ]
