ADM1026
Table 46. Register 21h, Status Register 2 (Power-On Default 00h)
R/W
Bit Name
Description
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
±, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion
cycle;0 otherwise.
0
±
2
3
4
5
6
7
AIN0 Status = 0
R
AIN± Status = 0
AIN2 Status = 0
AIN3 Status = 0
AIN4 Status = 0
AIN5 Status = 0
AIN6 Status = 0
AIN7 Status = 0
R
R
R
R
R
R
R
Table 47. Register 22h, Status Register 3 (Power-On Default 00h)
R/W
Bit
0
±
2
3
4
5
6
7
Name
Description
FAN0 Status ± = 0
FAN± Status ± = 0
FAN2 Status ± = 0
FAN3 Status ± = 0
FAN4 Status ± = 0
FAN5 Status ± = 0
FAN6 Status ± = 0
FAN7 Status ± = 0
R
R
R
R
R
R
R
R
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
±, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.
Table 48. Register 23h, Status Register 4 (Power-On Default 00h)
Bit Name
R/W
Description
0
Int Temp Status = 0
R
±, if Int value is above the high limit or below the low limit on the previous conversion cycle, 0
otherwise. This bit is set (once only) if a THERM mode is engaged as a result of int temperature
readings exceeding the Int THERM limit. This bit is also set (once only) if THERM mode is disengaged
as a result of internal temperature readings going 5°C below Int THERM limit.
±
2
3
VBAT Status = 0
AIN8 Status = 0
R
R
R
±, if VBAT value is above the high limit or below the low limit on the previous conversion cycle,
0 otherwise.
±, if AIN8 value is above the high limit or below the low limit on the previous conversion cycle,
0 otherwise.
This bit is set (once only) if a THERM mode is engaged as a result of temperature readings
exceeding the THERM limits on any channel. This bit is also set (once only) if THERM mode is
disengaged as a result of temperature readings going 5°C below THERM limits on any channel.
THERM Status = 0
4
AFC Status = 0
R
This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC) mode as a
result of a temperature reading exceeding TMIN on any channel. This bit is also set (once only) if the
fan turns off when in automatic fan speed control mode.
5
6
7
Unused
CI Status = 0
GPIO±6 Status = 0
R
R
R
Unused. Reads back 0.
This bit latches a chassis intrusion event.
When GPIO±6 is configured as an input, this bit is set when GPIO±6 is asserted. (Asserted may be
active high or active low depending on the setting in GPIO configuration register.)
R/W
When GPIO±6 is configured as an output, setting this bit asserts GPIO±6. (Asserted may be active
high or active low depending on setting in GPIO configuration register.)
Rev. A | Page 45 of 56
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