ADM1026
Table 38. Register 19h, Mask Register 2 (Power-On Default 00h)
Bit
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0
AIN0 Mask = 0
AIN± Mask = 0
AIN2 Mask = 0
AIN3 Mask = 0
AIN4 Mask = 0
AIN5 Mask = 0
AIN6 Mask = 0
AIN7 Mask = 0
When this bit is set, interrupts generated on the AIN0 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN± voltage channel are masked out.
When this bit is set, interrupts generated on the AIN2 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN3 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN4 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN5 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN6 voltage channel are masked out.
When this bit is set, interrupts generated on the AIN7 voltage channel are masked out.
±
2
3
4
5
6
7
Table 39. Register 1Ah, Mask Register 3 (Power-On Default 00h)
Bit
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0
FAN0 Mask = 0
FAN± Mask = 0
FAN2 Mask = 0
FAN3 Mask = 0
FAN4 Mask = 0
FAN5 Mask = 0
FAN6 Mask = 0
FAN7 Mask = 0
When this bit is set, interrupts generated on the FAN0 tach channel are masked out.
When this bit is set, interrupts generated on the FAN± tach channel are masked out.
When this bit is set, interrupts generated on the FAN2 tach channel are masked out.
When this bit is set, interrupts generated on the FAN3 tach channel are masked out.
When this bit is set, interrupts generated on the FAN4 tach channel are masked out.
When this bit is set, interrupts generated on the FAN5 tach channel are masked out.
When this bit is set, interrupts generated on the FAN6 tach channel are masked out.
When this bit is set, interrupts generated on the FAN7 tach channel are masked out.
±
2
3
4
5
6
7
Table 40. Register 1Bh, Mask Register 4 (Power-On Default 00h)
Bit Name R/W Description
0
±
2
3
4
5
6
7
Int Temp Mask = 0
R/W When this bit is set, interrupts generated on the internal temperature channel are masked out.
R/W When this bit is set, interrupts generated on the VBAT voltage channel are masked out.
R/W When this bit is set, interrupts generated on the AIN8 voltage channel are masked out.
R/W When this bit is set, interrupts generated from THERM events are masked out.
R/W When this bit is set, interrupts generated from automatic fan control events are masked out.
R/W Unused. Reads back 0.
VBAT Mask = 0
AIN8 Mask = 0
THERM Mask = 0
AFC Mask = 0
Unused
CI Mask = 0
R/W When this bit is set, interrupts generated by the chassis intrusion input are masked out.
R/W When this bit is set, interrupts generated on the GPIO±6 channel are masked out.
GPIO±6 Mask = 0
Table 41. Register 1Ch, Mask Register 5 (Power-On Default 00h)
Bit
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0
GPIO0 Mask = 0
GPIO± Mask = 0
GPIO2 Mask = 0
GPIO3 Mask = 0
GPIO4 Mask = 0
GPIO5 Mask = 0
GPIO6 Mask = 0
GPIO7 Mask = 0
When this bit is set, interrupts generated on the GPIO0 channel are masked out.
When this bit is set, interrupts generated on the GPIO± channel are masked out.
When this bit is set, interrupts generated on the GPIO2 channel are masked out.
When this bit is set, interrupts generated on the GPIO3 channel are masked out.
When this bit is set, interrupts generated on the GPIO4 channel are masked out.
When this bit is set, interrupts generated on the GPIO5 channel are masked out.
When this bit is set, interrupts generated on the GPIO6 channel are masked out.
When this bit is set, interrupts generated on the GPIO7 channel are masked out.
±
2
3
4
5
6
7
Rev. A | Page 43 of 56
ADI [ ADI ]
