ADM1026
Table 31. Register 12h, TDM2 Temperature TMIN (Power-On Default 40h, 64°C)
Bit
Name
R/W Description
7–0
TDM2 Temp TMIN
R/W This register contains the TMIN value for automatic fan speed control based on the TDM2 temperature
channel.
Table 32. Register 13h, EEPROM Register 3 (Power-On Default 00h)
R/W
Bit
0
Name
Description
R/W
R/W
R/W
R/W
Once
R/W
R/W
R/W
R/W
Read
Setting this bit puts the EEPROM into read mode.
Setting this bit puts the EEPROM in write (program) mode.
Setting this bit puts the EEPROM into erase mode.
±
Write
2
Erase
3
Write Protect
Setting this bit protects the EEPROM against accidental writing or erasure. This bit is write-once and
can only be cleared by a power-on reset.
4
5
6
Test Mode Bit 0
Test Mode Bit ±
Test Mode Bit 2
Clock Extend
Test mode bits. For factory use only
Test mode bits. For factory use only.
Test mode bits. For factory use only
Setting this bit enables SMBus clock extension. The ADM±026 can pull SCL low to extend the clock
pulse if it cannot accept any more data. It is recommended to set this bit to ± to extend the clock
pulse during repeated EEPROM write or block write operations.
7
Table 33. Register 14h, Manufacturer’s Test Register 1 (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Manufacturer’s Test ± R/W
This register is used by the manufacturer for test purposes. It should not be read from or written
to in normal operation.
Table 34. Register 15h, Manufacturer’s Test Register 2 (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Manufacturer’s Test 2 R/W
This register is used by the manufacturer for test purposes. It should not be read from or written
to in normal operation.
Table 35. Register 16h, Manufacturer’s ID (Power-On Default 41h)
Bit
Name
R/W Description
7–0
Manufacturer’s ID Code
R
This register contains the manufacturer’s ID code.
Table 36. Register 17h, Revision Register (Power-On Default 4xh)
Bit
Name
R/W Description
3–0
Minor Revision Code
R
This nibble contains the manufacturer’s code for minor revisions to the device. Rev ± = 0h,
Rev 2 = ±h, and so on.
7–4
Major Revision Code
R
This nibble denotes the generation of the device. For the ADM±026, this nibble reads 4h.
Table 37. Register 18h, Mask Register 1 (Power-On Default 00h)
Bit Name
R/W Description
0
±
2
3
4
5
6
7
Ext± Temp Mask = 0
R/W When this bit is set, interrupts generated on the Ext± temperature channel are masked out.
R/W When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out.
R/W When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are masked out.
R/W When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are masked out.
R/W When this bit is set, interrupts generated on the +5 V voltage channel are masked out.
R/W When this bit is set, interrupts generated on the VCCP voltage channel are masked out.
R/W When this bit is set, interrupts generated on the +±2 V voltage channel are masked out.
R/W When this bit is set, interrupts generated on the −±2 V voltage channel are masked out.
Ext2 Temp
3.3 V STBY Mask = 0
3.3 V MAIN Mask = 0
+5 V Mask = 0
VCCP Mask = 0
+±2 V Mask = 0
−±2 V Mask = 0
Rev. A | Page 42 of 56
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