ADM1026
Table 69. Register 38h, FAN0 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN0 Value
R
This register contains the measured value of the FAN0 tach input channel.
Table 70. Register 39h, FAN1 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN± Value
R
This register contains the measured value of the FAN± tach input channel.
Table 71. Register 3Ah, FAN2 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN2 Value
R
This register contains the measured value of the FAN2 tach input channel.
Table 72. Register 3Bh, FAN3 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN3 Value
R
This register contains the measured value of the FAN3 tach input channel.
Table 73. Register 3Ch, FAN4 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN4 Value
R
This register contains the measured value of the FAN4 tach input channel.
Table 74. Register 3Dh, FAN5 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN5 Value
R
This register contains the measured value of the FAN5 tach input channel.
Table 75. Register 3Eh, FAN6 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN6 Value
R
This register contains the measured value of the FAN6 tach input channel.
Table 76. Register 3Fh, FAN7 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
FAN7 Value
R
This register contains the measured value of the FAN7 tach input channel.
Table 77. Register 40h, Ext1 High Limit (Power-On Default 64h/100°C)
Bit
Name
R/W
Description
7–0
Ext± High Limit
R/W
This register contains the high limit of the Ext± Temp channel.
Table 78. Register 41h, Ext2/AIN9 High Limit (Power-On Default 64h/100°C)
Bit
Name
R/W
Description
7–0
Ext2 Temp/ AIN9 High
Limit
R/W
This register contains the high limit of the Ext2 Temp/AIN9 channel depending on which one
is configured.
Table 79. Register 42h, 3.3 V STBY High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
3.3 V STBY High Limit
R/W
This register contains the high limit of the 3.3 V STBY analog input channel.
Table 80. Register 43h, 3.3 V MAIN High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
3.3 V MAIN High Limit
R/W
This register contains the high limit of the 3.3 V MAIN analog input channel.
Table 81. Register 44h, +5 V High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
+5 V High Limit
R/W
This register contains the high limit of the +5 V analog input channel.
Table 82. Register 45h, VCCP High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
VCCP High Limit
R/W
This register contains the high limit of the VCCP analog input channel.
Rev. A | Page 49 of 56
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