ADM1026
Table 49. Register 24h, Status Register 5 (Power-On Default 00h)
Bit Name
R/W1
Description
0
±
2
3
4
5
6
7
GPIO0 Status = 0
R
When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted. (Asserted may be
active high or active low depending on setting of Bit ± in GPIO Configuration Register ±.)
When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted may be active high
or active low depending on setting of Bit ± in GPIO Configuration Register ±.)
R/W
R
GPIO± Status = 0
GPIO2 Status = 0
GPIO3 Status = 0
GPIO4 Status = 0
GPIO5 Status = 0
GPIO6 Status = 0
GPIO7 Status = 0
When GPIO± is configured as an input, this bit is set when GPIO± is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register ±.)
When GPIO± is configured as an output, setting this bit asserts GPIO±. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register ±.)
R/W
R
When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register ±.)
When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register ±.)
R/W
R
When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register ±.)
When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register ±.)
R/W
R
When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted. (Asserted may be
active high or active low depending on setting of Bit ± in GPIO Configuration Register 2.)
When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted may be active high
or active low depending on setting of Bit ± in GPIO Configuration Register 2.)
R/W
R
When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register 2.)
When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register 2.)
R/W
R
When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 2.)
When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 2.)
R/W
R
When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)
R/W
When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)
± GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Rev. A | Page 46 of 56
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