ADM1026
Table 50. Register 25h, Status Register 6 (Power-On Default 00h)
R/W1
Bit Name
Description
When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted. (Asserted may be active
high or active low depending on setting of Bit ± in GPIO Configuration Register 3.)
When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted may be active high or
active low depending on setting of Bit ± in GPIO Configuration Register 3.)
0
±
2
3
4
5
6
7
GPIO8 Status = 0
R
R/W
When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted. (Asserted may be active
high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.)
When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted may be active high or
active low depending on setting of Bit 3 in GPIO Configuration Register 3.)
GPIO9 Status = 0
GPIO±0 Status = 0
GPIO±± Status = 0
GPIO±2 Status = 0
GPIO±3 Status = 0
GPIO±4 Status = 0
GPIO±5 Status = 0
R
R/W
When GPIO±0 is configured as an input, this bit is set when GPIO±0 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)
When GPIO±0 is configured as an output, setting this bit asserts GPIO±0. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)
R
R/W
When GPIO±± is configured as an input, this bit is set when GPIO±± is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)
When GPIO±± is configured as an output, setting this bit asserts GPIO±±. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)
R
R/W
When GPIO±2 is configured as an input, this bit is set when GPIO±2 is asserted. (Asserted may be
active high or active low depending on setting of Bit ± in GPIO Configuration Register 4.)
When GPIO±2 is configured as an output, setting this bit asserts GPIO±2. (Asserted may be active high
or active low depending on setting of Bit ± in GPIO Configuration Register 4.)
R
R/W
When GPIO±3 is configured as an input , this bit is set when GPIO±3 is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)
When GPIO±3 is configured as an output, setting this bit asserts GPIO±3. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)
R
R/W
When GPIO±4 is configured as an input , this bit is set when GPIO±4 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)
When GPIO±4 is configured as an output, setting this bit asserts GPIO±4. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)
R
R/W
When GPIO±5 is configured as an input, this bit is set when GPIO±5 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)
R
When GPIO±5 is configured as an output, setting this bit asserts GPIO±5. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)
R/W
± GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Table 51. Register 26h, VBAT Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
VBAT Value
R
This register contains the measured value of the VBAT analog input channel.
Table 52. Register 27h, AIN8 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN8 Value
R
This register contains the measured value of the AIN8 analog input channel.
Table 53. Register 28h, EXT1 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Ext± Value
R
This register contains the measured value of the Ext± Temp channel.
Table 54. Register 29h, EXT2/AIN9 Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Ext2 Temp/ AIN9 Low Limit
R
This register contains the measured value of the Ext2 Temp/AIN9 channel depending on
which bit is configured.
Rev. A | Page 47 of 56
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