ADM1026
Table 42. Register 1Dh, Mask Register 6 (Power-On Default 00h)
Bit
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0
GPIO8 Mask = 0
GPIO9 Mask = 0
GPIO±0 Mask = 0
GPIO±±Mask = 0
GPIO±2 Mask = 0
GPIO±3 Mask = 0
GPIO±4 Mask = 0
GPIO±5 Mask = 0
When this bit is set, interrupts generated on the GPIO8 channel are masked out.
When this bit is set, interrupts generated on the GPIO9 channel are masked out.
When this bit is set, interrupts generated on the GPIO±0 channel are masked out.
When this bit is set, interrupts generated on the GPIO±± channel are masked out.
When this bit is set, interrupts generated on the GPIO±2 channel are masked out.
When this bit is set, interrupts generated on the GPIO±3 channel are masked out.
When this bit is set, interrupts generated on the GPIO±4 channel are masked out.
When this bit is set, interrupts generated on the GPIO±5 channel are masked out.
±
2
3
4
5
6
7
Table 43. Register 1Eh, INT Temp Offset (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Int Temp Offset
R/W
This register contains the offset value for the internal temperature channel, a twos complement
result before it is stored or compared to limits. In this way, a sort of one-point calibration can be
done whereby the whole transfer function of the channel can be moved up or down. From a
software point of view, this may be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change for any reason (for instance from one
chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and
so on.
Table 44. Register 1Fh, INT Temp Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Int Temp Value
R
This register contains the measured value of the internal temperature channel.
Table 45. Register 20h, Status Register 1 (Power-On Default 00h)
Bit Name
R/W
Description
0
Ext± Temp Status = 0
R
±, if Ext± value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext± temp readings
exceeding the Ext± THERM limit. This bit is also set (once only) if THERM mode is disengaged as a
result of Ext± temperature readings going 5°C below Ext± THERM limit.
±
Ext2 Temp Status = 0
R
±, if Ext 2 value (or AIN9 if in voltage measurement mode) is above the /AIN9 status = 0 high limit or
below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a
THERM mode is engaged as a result of Ext2 temperature readings exceeding the Ext2 THERM limit.
This bit is also set (once only) if THERM mode is disengaged as a result of Ext2 temperature readings
going 5°C below Ext2 THERM limit.
2
3
4
5
6
7
3.3 V STBY Status = 0
3.3 V MAIN Status = 0
+5 V Status = 0
R
R
R
R
R
R
±, if 3.3 V STBY value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
±, if 3.3 V MAIN value is above the high limit or below the low limit on the previous conversion
cycle; 0 otherwise.
±, if +5 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
±, if VCCP value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
VCCP Status = 0
+±2 V Status = 0
−±2 V Status = 0
±, if +±2 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
±, if −±2 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
Rev. A | Page 44 of 56
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