AD1846
Clock a nd Da ta For m a t Register (IXA3:0 = 8)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
8
res
FM T
C/L
S/M
C FS2
C FS1
C FS0
CSS
The contents of the Clock and Data Format Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state.
Write attempts to this register when the AD1846 is not in the MCE state will not be successful.
CSS
Clock Source Select. T hese bits select the crystal clock source which will be used for the audio sample rates.
0
1
XT AL1 (24.576 MHz)
XT AL2 (16.9344 MHz)
CFS2:0 Clock Frequency Divide Select. T hese bits select the audio sample rate frequency. T he actual audio sample rate depends
on which crystal clock source is selected and the frequency of that source.
D ivide
Factor
XTAL1
24.576 MH z
XTAL2
16.9344 MH z
CFS
0
1
2
3
4
5
6
7
3072
1536
896
768
448
384
512
2560
8.0 kHz
16.0 kHz
5.5125 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.615 kHz
27.42857 kHz
32.0 kHz
Not Supported
Not Supported
48.0 kHz
9.6 kHz
Note that the AD1846’s internal oscillators can be driven by external clock sources at the crystal input pins. If an external
clock source is applied, it will be divided down by the selected Divide Factor. It need not be at the recommended crystal
frequencies.
S/M
C/L
Stereo/Mono Select. T his bit determines how the audio data streams are formatted. Selecting stereo will result with alter-
nating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels.
Mono capture only captures data from the left audio channel.
0
1
Mono
Stereo
Companded/Linear Select. T his bit selects between a linear digital representation of the audio signal or a nonlinear, com-
panded format for all input and output data. T he type of linear PCM or the type of companded format is defined by the
FMT bits.
0
1
Linear PCM
Companded
FMT
Format Select. T his bit defines the format for all digital audio input and outputs based on the state of the C/L bit.
Linear P CM (C/L = 0)
Com panded (C/L = 1)
0
1
8-bit Unsigned PCM
16-bit T wos-Complement PCM
8-bit µ-law Companded
8-bit A-law Companded
res
Reserved for future expansion. Always write a zero to this bit.
T his register’s initial state after reset is “x000 0000.”
REV. A
–17–
ADI [ ADI ]
