AD1846
Digita l Mix Contr ol Register (IXA3:0 = 13)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
13
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
res
D M E
DME
Digital Mix Enable. T his bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the
data from the ADCs are digitally mixed with other data being delivered to the DACs (regardless of whether or not play-
back [PEN] is enabled, i.e., set). If capture is enabled (CEN set) and there is a capture overrun (COR), then the last
sample captured before overrun will be used for the digital mix. If playback is enabled (PEN set) and there is a playback
underrun (PUR), then a midscale zero will be added to the digital mix data.
0
1
Digital mix disabled (muted)
Digital mix enabled
res
Reserved for future expansion. Always write a zero to this bit.
DMA5:0 Digital Mix Attenuation. T hese bits determine the attenuation of the ADC data in mixing with the DAC input. Each at-
tenuate step is –1.5 dB ranging to –94.5 dB.
T his register’s initial state after reset is “0000 00x0.”
DMA BASE COUNT REGISTERS (IXA3:0 = 14 & 15)
T he DMA Base Count Registers in the AD1846 simplify integration of the AD1846 in ISA systems. T he ISA DMA controller re-
quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. T he programmable DMA Base
Count Registers will allow such interrupts to occur.
T he Base Count Registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt
(INT ) pin. T o load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both
Base Count Registers to load into the Current Count Register. Once AD1846 transfers are enabled, each sample period the Current
Count Register will decrement until zero count is reached. T he next sample period after zero will generate the interrupt and reload
the Current Count Register with the values in the Base Count Registers. T he interrupt is cleared by a write to the Status Register.
T he Host Interrupt Pin (INT ) will go HI during the sample period in which the Current Count Register underflows when Interrupt
Enable (IEN) is set. T he Host Interrupt Pin (INT ) will go LO when the Interrupt Status Bit (INT ) is cleared. [Note that both the
Host Interrupt Pin and the Interrupt Status Bit have the same name (INT )].
T he Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled and also either the
T ransfer Request Disable (T RD) bit or the Interrupt Status (INT ) bit are zero. Note that the internal INT bit will become one on
counter underflow even if the external interrupt pin is not enabled, i.e., IEN is zero. T he Current Count Register is decremented in
both PIO and DMA data transfer modes.
Upper Ba se Count Register (IXA3:0 = 14)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
14
U B7
U B6
U B5
U B4
U B3
U B2
U B1
U B0
UB7:0
Upper Base Count. T his byte is the upper byte of the base count register containing the eight most significant bits of the
16-bit base register. Reads from this register return the same value which was written. T he current count contained in the
counters can not be read.
T his register’s initial state after reset is “0000 0000.”
Lower Upper Ba se Count Register (IXA3:0 = 15)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
15
LB7
LB6
LB5
LB4
LB3
LB2
LB1
LB0
LB7:0
Lower Base Count. T his byte is the lower byte of the base count register containing the eight least significant bits of the
16-bit base register. Reads from this register return the same value which was written. T he current count contained in the
counters cannot be read.
T his register’s initial state after reset is “0000 0000.”
–20–
REV. A
ADI [ ADI ]
