AD1846
Inter fa ce Configur a tion Register (IXA3:0 = 9)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
9
CPIO
PPIO
res
res
ACAL
SD C
C EN
P EN
The contents of the Interface Configuration Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state.
Write attempts to this register when the AD1846 is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may al-
ways be written.
PEN
CEN
SDC
Playback Enable. T his bit will enable the playback of data in the format selected. T he AD1846 will generate PDRQ and
respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Programmed I/O (PIO)
playback mode. PEN may be set and reset without setting the MCE bit.
0
1
Playback disabled (PDRQ and PIO Playback Data Register inactive)
Playback enabled
Capture Enable. T his bit will enable the capture of data in the format selected. T he AD1846 will generate CDRQ and re-
spond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO capture mode. CEN
may be set and reset without setting the MCE bit.
0
1
Capture disabled (CDRQ and PIO Capture Data Register inactive)
Capture enabled
Single DMA Channel. T his bit will force both capture and playback DMA requests to occur on the Playback DMA chan-
nel. T he Capture DMA CDRQ pin will be LO. T his bit will allow the AD1846 to be used with only one DMA channel.
Simultaneous capture and playback cannot occur in this mode. Should both capture and playback be enabled
(CEN = PEN = 1) in the mode, only playback will occur. See “Data and Control T ransfers” for further explanation.
0
1
Dual DMA channel mode
Single DMA channel mode
ACAL
Autocalibrate Enable. T his bit determines whether the AD1846 performs an autocalibrate whenever the PWRDWN pin is
deasserted or from the Mode Change Enable (MCE) bit being reset. ACAL is normally set. See “Autocalibration” below
for a description of a complete autocalibration sequence.
0
1
No autocalibration
Autocalibration after power down/reset or mode change
res
Reserved for future expansion. Always write zeros to these bits.
PPIO
Playback PIO Enable. T his bit determines whether the playback data is transferred via DMA or PIO.
0
1
DMA transfers only
PIO transfers only
CPIO
Capture PIO Enable. T his bit determines whether the capture data is transferred via DMA or PIO.
0
1
DMA transfers only
PIO transfers only
T his register’s initial state after reset is “00xx 1000.”
Pin Contr ol Register (IXA3:0 = 10)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
10
XC T L1
XC T L0
res
res
res
res
IEN
res
res
Reserved for future expansion. Always write zeros to these bits.
IEN
Interrupt Enable. T his bit enables the interrupt pin. T he Interrupt Pin will go active HI when the number of samples pro-
grammed in the Base Count Register is reached.
0
1
Interrupt disabled
Interrupt enabled
XCT L1:0 External Control. T he state of these independent bits is reflected on the respective XCT L1:0 pins of the AD1846.
0
1
T T L Logic LO on XCT L1:0 pins
T T L Logic HI on XCT L1:0 pins
T his register’s initial state after reset is “00xx xx0x.”
–18–
REV. A
ADI [ ADI ]
