AD1846
Sta tus Register (ADR1:0 = 2)
AD R1:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
2
C U /L
CL/R
CRDY
SOUR
PU /L
PL/R
PRD Y
IN T
INT
Interrupt Status. T his sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. T his bit is cleared
by any host write of any value to this register. T he IEN bit of the Pin Control Register determines whether the state of this
bit is reflected on the INT pin of the AD1846. T he only interrupt condition supported by the AD1846 is generated by the
underflow of the DMA Current Count Register.
0
1
Interrupt pin inactive
Interrupt pin active
PRDY
PL/R
Playback Data Register Ready. T he PIO Playback Data Register is ready for more data. T his bit should only be used when
direct programmed I/O data transfers are desired. T his bit is read only.
0
1
DAC data is still valid. Do not overwrite.
DAC data is stale. Ready for next host data write value.
Playback Left/Right Sample. T his bit indicates whether the PIO playback data needed is for the right channel DAC or left
channel DAC. T his bit is read only.
0
1
Right channel needed
Left channel or mono
PU/L
Playback Upper/Lower Byte. T his bit indicates whether the PIO playback data needed is for the upper or lower byte of the
channel. T his bit is read only.
0
1
Lower byte needed
Upper byte needed or any 8-bit mode
SOUR
CRDY
Sample Over/Underrun. T his bit indicates that the most recent sample was not serviced in time and therefore either a cap-
ture overrun (COR) or playback underrun (PUR) has occurred. T he bit indicates an overrun for ADC capture and an
underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be determined by
reading COR and PUR. T his bit changes on a sample-by-sample basis. T his bit is read only.
Capture Data Ready. T he PIO Capture Data Register contains data ready for reading by the host. T his bit should only be
used when direct programmed I/O data transfers are desired. T his bit is read only.
0
1
ADC data is stale. Do not reread the information.
ADC data is fresh. Ready for next host data read.
CL/R
CU/L
Capture Left/Right Sample. T his bit indicates whether the PIO capture data waiting is for the right channel ADC or left
channel ADC. T his bit is read only.
0
1
Right channel
Left channel or mono
Capture Upper/Lower Byte. T his bit indicates whether the PIO capture data ready is for the upper or lower byte of the
channel. T his bit is read only.
0
1
Lower byte ready
Upper byte ready or any 8-bit mode
T he PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. T he host may access this regis-
ter while the bits are transitioning. T he host read may return a zero value just as these bits are changing, for example. A “1” value
would not be read until the next host access.
T his registers’s initial state after reset is “1100 1100.”
REV. A
–13–
ADI [ ADI ]
