AD1846
PIO Da ta Register s (ADR1:0 = 3)
AD R1:0
D ata 7
C D 7
P D 7
D ata 6
C D 6
P D 6
D ata 5
C D 5
P D 5
D ata 4
C D 4
P D 4
D ata 3
C D 3
P D 3
D ata 2
C D 2
P D 2
D ata 1
C D 1
P D 1
D ata 0
C D 0
P D 0
3
3
T he PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0).
Reads will receive data from the PIO Capture Data Register (CD7:0).
During AD1846 initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read
“1000 0000 (80h).”
CD7:0
PIO Capture Data Register. T his is the control register where capture data is read during programmed I/O data transfers.
T he reading of this register will increment the state machine so that the following read will be from the next appropriate
byte in the sample. T he exact byte which is next to be read can be determined by reading the Status Register. Once all rel-
evant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received
from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the sample.
Until a new sample is received, reads from this register will return the most significant byte of the sample.
PD7:0
PIO Playback Data Register. T his is the control register where playback data is written during programmed I/O data
transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will be to
the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ig-
nored. T he state machine is reset when the current sample is sent to the DACs.
Indir ect Contr ol Register D efinitions
T he following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed
by a read/write to the Indexed Data Register (ADR1:0 = 1).
Left Input Contr ol (IXA3:0 = 0)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0
LSS1
LSS0
LM GE
res
LIG 3
LIG 2
LIG 1
LIG 0
LIG3:0 Left input gain select. T he least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
res
Reserved for future expansion. Always write a zero to this bit.
LMGE
Left Input Microphone Gain Enable. Setting this bit will enable the +18 dB digital gain of the left mic input signal.
LSS1:0 Left Input Source Select. T hese bits select the input source for the left gain stage preceding the left ADC.
0
1
2
3
Left Line Source Selected
Left Auxiliary 1 Source Selected
Left Microphone Source Selected
Left Line Post-Mixed DAC Output Source Selected
T his register’s initial state after reset is “000x 0000.”
–14–
REV. A
ADI [ ADI ]
