AD1846
Test a nd Initia liza tion Register (IXA3:0 = 11)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
11
COR
PU R
ACI
DRS
ORR1
ORR0
ORL1
ORL0
ORL1:0 Overrange Left Detect. T hese bits indicate the overrange on the left input channel. T his bit changes on a sample-by-
sample basis. T his bit is read only.
0
1
2
3
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
ORR1:0 Overrange Right Detect. T hese bits indicate the overrange on the right input channel. T his bit changes on a sample-by-
sample basis. T his bit is read only.
0
1
2
3
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
DRS
ACI
Data Request Status. T his bit indicates the current status of the PDRQ and CDRQ pins of the AD1846.
0
1
CDRQ and PDRQ are presently inactive (LO)
CDRQ or PDRQ are presently active (HI)
Autocalibrate-In-Progress. T his bit indicates the state of autocalibration or a recent exit from Mode Change Enable
(MCE). T his bit is read only.
0
1
Autocalibration is not in progress
Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods
PUR
COR
Playback Underrun. T his bit is set when playback data has not arrived from the host in time to be played. As a result, a
midscale value will be sent to the DACs. T his bit changes on a sample by sample basis.
Capture Overrun. T his bit is set when the capture data has not been read by the host before the next sample arrives. T he
sample being read will not be overwritten by the new sample. T he new sample will be ignored. T his bit changes on a
sample by sample basis.
T he occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. T he SOUR bit
is the logical OR of the COR and PUR bits. T his enables a polling host CPU to detect an overrun/underrun condition while checking
other status bits.
T his register’s initial state after reset is “0000 0000.”
Miscella neous Contr ol Register (IXA3:0 = 12)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
12
res
res
res
res
ID 3
ID 2
ID 1
ID 0
res
Reserved for future expansion. T he bits are read only. Do not write to these bits.
ID3:0
AD1846 Revision ID. T hese four bits define the revision level of the AD1846. T he AD1846 is designated
ID = “1010.” Revisions increment by one LSB. T hese bits are read only.
T his register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use.
REV. A
–19–
ADI [ ADI ]
