AD1846
CONTROL REGISTERS
Control Register Architecture
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Clock and Data Format
Interface Configuration
Pin Control
Test and Initialization
Miscellaneous Information
Digital Mix
Upper Base Count
Lower Base Count
The AD1846 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 21 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is a playback or a capture.)
ADR1:0
0
1
2
3
Register Name
Index Address Register
Indexed Data Register
Status Register
PIO Data Registers
Figure 4. Direct Register Map
A write to or a read from the Indexed Data Register will access
the indirect register which is indexed by the value most recently
written to the Index Address Register. The Status Register and
the PIO Data Register are always accessible directly, without in-
dexing. The 16 indirect registers are indexed in Figure 5.
Figure 5. Indirect Register Map
A detailed map of all direct and indirect register contents is
summarized for reference as follows:
Direct Registers:
ADR1:0
Data 7
0
INIT
1
IXD7
2
CU/L
3
CD7
3
PD7
Data 6
MCE
IXD6
CL/R
CD6
PD6
Data 5
TRD
IXD5
CRDY
CD5
PD5
Data 4
res
IXD4
SOUR
CD4
PD4
Data 3
IXA3
IXD3
PU/L
CD3
PD3
Data 2
IXA2
IXD2
PL/R
CD2
PD2
Data 1
IXA1
IXD1
PRDY
CD1
PD1
Data 0
IXA0
IXD0
INT
CD0
PD0
Indirect Registers:
IXA3:0
Data 7
0
LSS1
1
RSS1
2
LMX1
3
RMX1
4
LMX2
5
RMX2
6
LDM
7
RDM
8
res
9
CPIO
10
XCTL1
11
COR
12
res
13
DMA5
14
UB7
15
LB7
Data 6
LSS0
RSS0
res
res
res
res
res
res
FMT
PPIO
XCTL0
PUR
res
DMA4
UB6
LB6
Data 5
LMGE
RMGE
res
res
res
res
LDA5
RDA5
C/L
res
res
ACI
res
DMA3
UB5
LB5
Data 4
res
res
LX1A4
RX1A4
LX2A4
RX2A4
LDA4
RDA4
S/M
res
res
DRS
res
DMA2
UB4
LB4
Data 3
LIG3
RIG3
LX1A3
RX1A3
LX2A3
RX2A3
LDA3
RDA3
CFS2
ACAL
res
ORR1
ID3
DMA1
UB3
LB3
Data 2
LIG2
RIG2
LX1A2
RX1A2
LX2A2
RX2A2
LDA2
RDA2
CFS1
SDC
res
ORR0
ID2
DMA0
UB2
LB2
Data 1
LIG1
RIG1
LX1A1
RX1A1
LX2A1
RX2A1
LDA1
RDA1
CFS0
CEN
IEN
ORL1
ID1
res
UB1
LB1
Data 0
LIG0
RIG0
LX1A0
RX1A0
LX2A0
RX2A0
LDA0
RDA0
CSS
PEN
res
ORL0
ID0
DME
UB0
LB0
Figure 6. Register Summary
Note that the only sticky bit in any of the AD1846 control registers is the interrupt (INT) bit. All other bits change with every
sample period.
REV. A
–11–
AD [ ANALOG DEVICES ]
