AD1846
Direct Control Register Definitions
Index Register (ADR1:0 = 0)
ADR1:0
Data 7
Data 6
0
INIT
MCE
Data 5
TRD
Data 4
res
Data 3
IXA3
Data 2
IXA2
Data 1
IXA1
Data 0
IXA0
IXA3:0
res
TRD
Index Address. These bits define the address of the AD1846 register accessed by the Indexed Data Register. These bits
are read/write.
Reserved for future expansion. Always write a zero to this bit.
Transfer Request Disable. This bit, when set, causes all data transfers to cease when the Interrupt Status (INT) bit of the
Status Register is set.
0
1
Transfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.
DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled.
Transfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either
PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the
time when TRD is set. After pending requests complete, midscale inputs will be internally generated for the
DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the TRD bit)
will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). The
DMA Current Counter Register will not decrement while both the TRD bit is set and the INT bit is a one.
MCE
Mode Change Enable. This bit must be set whenever the current functional mode of the AD1846 is changed. Specifically,
the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. The exceptions
are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be cleared at the com-
pletion of the desired register changes. The DAC outputs are automatically muted when the MCE bit is set. After MCE is
cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits.
Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to allow
the reference and all filters to settle. The ADCs will produce midscale values; the DACs’ analog output will be muted. All
converters are internally operating during these
≈128
sample cycles, and the AD1846 will expect playback data and will
generate (midscale) capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from the MCE state
regardless of whether or not ACAL was set. ACI will remain HI for these
≈128
sample cycles; system software should poll
this bit rather than count cycles.
Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS)
during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below.
INIT
AD1846 Initialization. This bit is set when the AD1846 is in a state which cannot respond to parallel bus cycles. This bit
is read only.
Immediately after reset and once the AD1846 has left the INIT state, the initial value of this register will be “0100 0000 (40h).”
During AD1846 initialization, this register cannot be written to and will always read “100x 0000 (80h).”
Indexed Data Register (ADR1:0 = 1)
ADR1:0
Data 7
Data 6
1
IXD7
IXD6
Data 5
IXD5
Data 4
IXD4
Data 3
IXD3
Data 2
IXD2
Data 1
IXD1
Data 0
IXD0
IXD7:0
Indexed Register Data. These bits contain the contents of the AD1846 register referenced by the Indexed Data Register.
During AD1846 initialization, this register cannot be written to and will always read as “1000 0000 (80h).”
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REV. A
AD [ ANALOG DEVICES ]
