AD14060/AD14060L
40 MH z–5 V
Max
40 MH z–3.3 V
P aram eter
Min
Min
Max
Units
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
7
5
100
3
25
8.75
5
100
3
ns
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
tCK
CLKIN
tCKH
tCKL
Figure 9. Clock Input
5 V
3.3 V
P aram eter
Reset
Min
Max
Min
Max
Units
Timing Requirements:
tWRST
tSRST
RESET Pulsewidth Low1
4tCK
4tCK
14 + DT /2
ns
ns
RESET Setup Before CLKIN High2 14 + DT /2
tCK
tCK
NOT ES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 10. Reset
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Inter r upts
Timing Requirements:
tSIR
tHIR
tIPW
IRQ2-0 Setup Before CLKIN High1
18 + 3DT /4
2 + tCK
18 + 3DT /4
2 + tCK
ns
ns
ns
IRQ2-0 Hold Before CLKIN High1
IRQ2-0 Pulsewidth2
11.5 + 3DT /4
11.5 + 3DT /4
NOT ES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2-0
tIPW
Figure 11. Interrupts
–16–
REV. A
ADI [ ADI ]
