AD14060/AD14060L
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Tim er
Switching Characteristic:
tDT EX
CLKIN High to T IMEXP
16
16
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 12. Tim er
5 V
3.3 V
P aram eter
Flags
Min
Max
Min
Max
Units
Timing Requirements:
tSFI
tHFI
tDWRFI
tHFIWR
FLAG2-0IN Setup Before CLKIN High1
FLAG2-0IN Hold After CLKIN High1
FLAG2-0IN Delay After RD/WR Low1
FLAG2-0IN Hold After RD/WR Deasserted1
8 + 5DT /16
0.5 – 5DT /16
8 + 5DT /16
0.5 – 5DT /16
ns
ns
ns
ns
4.5 + 7DT /16
4.5 + 7DT /16
0.5
0.5
Switching Characteristics:
tDFO
tHFO
tDFOE
tDFOD
FLAG2-0OUT Delay After CLKIN High
17
15
17
15
ns
ns
ns
ns
FLAG2-0OUT Hold After CLKIN High
CLKIN High to FLAG2-0OUT Enable
CLKIN High to FLAG2-0OUT Disable
4
3
4
3
NOT E
1Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tDFO
tDFOD
tHFO
FLAG2–0
OUT
FLAG OUTPUT
CLKIN
tHFI
tSFI
FLAG2–0
IN
tHFIWR
tDWRFI
RD, WR
FLAG INPUT
Figure 13. Flags
REV. A
–17–
ADI [ ADI ]
