AD14060/AD14060L
T he 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. T he pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
TARGET BO ARD CO NNECTO R FO R EZ-ICE P RO BE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. T he EZ-ICE probe
requires that the AD14060/AD14060L’s CLKIN (optional),
T MS, T CK, TRST, T DI, T DO, EMU and GND signals be
made accessible on the target system via a 14-pin connector (a
pin strip header) such as that shown in Figure 6. T he EZ-ICE
probe plugs directly onto this connector for chip-on-board emu-
lation. You must add this connector to your target board design
if you intend to use the ADSP-2106x EZ-ICE. T he length of
the traces between the connector and the AD14060/
T he BT MS, BT CK, BTRST and BT DI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
AD14060L’s JT AG pins should be as short as possible.
BTRST on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
1
3
5
2
4
6
EMU
GND
The JTAG signals are terminated on the EZ-ICE probe as follows:
KEY (NO PIN)
CLKIN (OPTIONAL)
TMS
Signal
Term ination
T MS
T CK
Driven through 22 Ω Resistor (16 µA–3.2 µA Driver)
Driven at 10 MHz through 22 Ω Resistor (16 µA–
3.2 µA Driver)
BTMS
7
9
8
TCK
BTCK
TRST
Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 kΩ resistor)
10
12
BTRST
TRST
9
T DI
Driven by 16 µA–3.2 µA Driver
11
T DO
One T T L Load, No T ermination
BTDI
GND
TDI
CLKIN One T T L Load, No T ermination (Optional Signal)
EMU
4.7 kΩ Pull-Up Resistor, One TTL Load (Open-Drain
13
14
TDO
Output from ADSP-2106x)
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE
TOP VIEW
software (after the invocation command).
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Em ulator (J um pers in Place)
Figure 7 shows JT AG scan path connections for the multi-
processor system.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
T he emulator only uses CLKIN when directed to perform
JTAG DEVICE
(OPTIONAL)
ADSP-2106x
#n
SHARC_A
SHARC_B
SHARC_C
SHARC_D
TDI
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 7. J TAG Scan Path Connections for the AD14060/AD14060L
REV. A
–12–
ADI [ ADI ]
