AD14060/AD14060L
Mem or y Read—Bus Master
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write – Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. T hese specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tDAD
tDRLD
tHDA
tHDRH
tDAAK
tDSAK
Address, Delay to Data Valid1, 4
17.5 + DT + W
11.5 + 5DT/8 + W
17.5 + DT + W
11.5 + 5DT/8 + W ns
ns
RD Low to Data Valid1
Data Hold from Address2
Data Hold from RD High2
ACK Delay from Address3, 4
ACK Delay from RD Low3
1
2.5
1
2.5
ns
ns
13.5 + 7DT/8 + W
7.5 + DT /2 + W
13.5 + 7DT/8 + W ns
7.5 + DT/2 + W
ns
Switching Characteristics:
tDRHA
tDARL
tRW
Address Hold After RD High
–0.5 + H
1.5 + 3DT /8
12.5 + 5DT/8 + W
8 + 3DT /8 + HI
–0.5 + H
ns
ns
ns
ns
ns
Address to RD Low4
1.5 + 3DT /8
12.5 + 5DT/8 + W
8 + 3DT /8 + HI
–0.5 + DT /4
RD Pulsewidth
RD High to WR, RD, DMAGx Low
tRWR
tSADADC Address Setup Before ADRCLK High4 –0.5 + DT /4
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOT ES
1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDAT I
.
2Data Hold: User must meet tHDA or tHDRH or synchronous spec tHDAT I. See System Hold T ime Calculation under T est Conditions for the calculation of hold times
given capacitive and dc loads.
3ACK Delay/Setup: User must meet tDSAK or tDAAK or synchronous specification tSACKC
.
4For MSx, SW, BMS, the falling edge is referenced.
ADDRESS
MSx, SW
BMS
tDRHA
tDARL
tRW
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Mem ory Read—Bus Master
REV. A
–18–
ADI [ ADI ]
