AD14060/AD14060L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
B Grade
Min
K Grade
P ar am eter
Max
Min
Max
Units
VDD
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating T emperature
4.75
3.15
–40
5.25
3.6
+100
4.75
3.15
0
5.25
3.6
+85
V
V
°C
T CASE
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Case
Test
5 V
3.3 V
Min Typ Max
P ar am eter
Tem p Level Test Condition
Min Typ Max
Units
VIH1
VIH2
VIL
VOH
VOL
IIH
High Level Input Voltage1
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
I
I
I
I
I
I
I
I
I
I
I
I
I
I
@ VDD = max
@ VDD = max
@ VDD = min
2.0
2.2
VDD + 0.5 2.0
VDD + 0.5 2.2
0.8
2.4
0.4
10
VDD + 0.5
VDD + 0.5
0.8
V
V
V
V
High Level Input Voltage2
Low Level Input Voltage1, 2
High Level Output Voltage3, 4
Low Level Output Voltage3, 4
High Level Input Current5, 6, 7
Low Level Input Current5
@ VDD = min, IOH = –2.0 mA4
@ VDD = min, IOL = 4.0 mA4
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V (5 V),
2 V (3.3 V)
4.1
0.4
10
10
150
600
10
10
350
1.5
V
µA
µA
µA
µA
µA
µA
µA
mA
IIL
IILP
10
Low Level Input Current6
150
600
10
10
350
1.5
IILPX4
IOZH
IOZL
IOZHP
IOZLC
IOZLA
Low Level Input Current7
T hree-State Leakage Current8, 9, 10, 14
T hree-State Leakage Current8, 11
T hree-State Leakage Current11
T hree-State Leakage Current12
T hree-State Leakage Current13
350
4.2
150
600
350
4.2
150
600
µA
mA
µA
µA
A
mA
pF
IOZLAR
IOZLS
T hree-State Leakage Current10
T hree-State Leakage Current9
Full
Full
Full
Full
Full
+25°C
I
I
I
IV
I
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
tCK = 25 ns, VDD = max
VDD = max
IOZLSX4 T hree-State Leakage Current14
IDDIN
IDDIDLE Supply Current (Idle)16
CIN
Input Capacitance17, 18
Supply Current (Internal)15
1.4 3.4
800
1.0 2.2
760
V
15
15
EXP LANATIO N O F TEST LEVELS
Test Level
I
100% Production T ested19
.
II
100% Production T ested at +25°C, and Sample T ested at Specified T emperatures.
III
IV
V
Sample T ested Only.
Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
Parameter is typical value only.
VI
All devices are 100% production tested at +25°C; sample tested at temperature extremes.
NOT ES
1 Applies to input and bidirectional pins: DAT A47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,
BR6-1, RPBA, CPAy, T FS0, T FSy1, RFS0, RFSy1, LyxDAT 3-0, LyxCLK, LyxACK, EBOOT A, LBOOT A, EBOOT BCD, LBOOT BCD, BMSA, BMSBCD, T MS,
T DI, T CK, HBR, DR0, DRy1, T CLK0, T CLKy1, RCLK0, RCLKy1.
2 Applies to input pins: CLKIN, RESET, TRST.
3 Applies to output and bidirectional pins: DAT A47-0, ADDR31-0, MS3-0 RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, T IMEXPy, HBG,
REDY, DMAG1, DMAG2, BR6-1, CPAy, DT O, DT y1, T CLK0, T CLKy1, RCLK0, RCLKy1, T FS0, T FSy1, RFS0, RFSy1 LyxDAT 3-0, LyxCLK, LyxACK,
BMSA, BMSBCD, T DO, EMU.
4 See Output Drive Currents for typical drive current capabilities.
5 Applies to input pins: SBTS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOT A, LBOOT A, EBOOT BCD, LBOOT BCD, CLKIN, RESET, T CK.
6 Applies to input pins with internal pull-ups: DR0, DRy1, T DI.
7Applies to bussed input pins with internal pull-ups: TRST, T MS.
8 Applies to three-statable pins: DAT A47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,
BMSA, BMSBCD, T DO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-
2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)
9 Applies to three-statable pins with internal pull-ups: DT y1, T CLKy1, RCLKy1.
10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11 Applies to three-statable pins with internal pull-downs: LyxDAT 3-0, LyxCLK, LyxACK.
12 Applies to CPAy pin.
13 Applies to ACK pin when keeper latch enabled.
14 Applies to bused three-statable pins with internal pull-ups: DT 0, T CLK0, RCLK0.
15 Applies to VDD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal
memory block, and one DMA transfer occurring from/to internal memory at t CK = 25 ns.
16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17 Applies to all signal pins.
18 Guaranteed but not tested.
19 Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
level. See T iming Specifications.
Specifications subject to change without notice.
REV. A
–14–
ADI [ ADI ]
