AD14060/AD14060L
Synchr onous Read/Wr ite—Bus Master
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). T he
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). T hese
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
5 V
Max
3.3 V
Max
P aram eter
Min
Min
Units
Timing Requirements:
tSSDAT I
tHSDAT I
tDAAK
tSACKC
tHACKC
Data Setup Before CLKIN
Data Hold After CLKIN
3 + DT /8
4 – DT /8
3 + DT /8
4 – DT /8
ns
ns
ACK Delay After Address, MSx, SW, BMS1, 2
ACK Setup Before CLKIN2
ACK Hold After CLKIN
13.5 + 7 DT/8 + W
13.5 + 7 DT/8 + W ns
6.5 + DT /4
–0.5 – DT /4
6.5 + DT /4
–0.5 – DT /4
ns
ns
Switching Characteristics:
tDADRO
tHADRO
tDPGC
tDRDO
tDWRO
Address, MSx, BMS, SW Delay After CLKIN1
8 – DT /8
8 – DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address, MSx, BMS, SW Hold After CLKIN
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
–1 – DT /8
9 + DT /8
–2 – DT /8
–1 – DT /8
9 + DT /8
–2 – DT /8
17 + DT /8
5 – DT /8
–3 – 3DT /16 5 – 3DT /16
17 + DT /8
5 – DT /8
–3 – 3DT /16 5 – 3DT /16
tDRWL
8 + DT /4
13.5 + DT /4
20 + 5DT /16
8 – DT /8
8 + DT /4
13.5 + DT /4
20 + 5DT /16
8 – DT /8
tSDDAT O
tDAT T R
tDADCCK
tADRCK
tADRCKH
tADRCKL
Data Disable After CLKIN 3
ADRCLK Delay After CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
0 – DT /8
4 + DT /8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
0 – DT /8
4 + DT /8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
11 + DT /8
11 + DT /8
W = (number of Wait states specified in WAIT register) × tCK
.
NOT ES
1For MSx, SW, BMS, the falling edge is referenced.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC
.
3See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
REV. A
–20–
ADI [ ADI ]
