AD14060/AD14060L
Mem or y Wr ite—Bus Master
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write–Bus
Master). If these timing requirements are met, the synchronous
read/write timing can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. T hese specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tDAAK
tDSAK
ACK Delay from Address, Selects1, 2
13.5 + 7DT/8 + W
7.5 + DT /2 + W
13.5 + 7DT/8 + W ns
ACK Delay from WR Low1
7.5 + DT /2 + W
ns
Switching Characteristics:
tDAWH
tDAWL
tWW
tDDWH
tDWHA
Address, Selects to WR Deasserted2
16.5 + 15DT/16 + W
2.5 + 3DT /8
16.5 + 15DT/16 + W
2.5 + 3DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address, Selects to WR Low2
WR Pulsewidth
12 + 9DT/16 + W
6.5 + DT /2 + W
–1 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4.5 + 3DT /8 + I
–1.5 + DT /16
12 + 9DT/16 + W
6.5 + DT /2 + W
–1 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4.5 + 3DT /8 + I
–1.5 + DT /16
Data Setup before WR High
Address Hold after WR Deasserted
tDAT RWH Data Disable after WR Deasserted3
tWWR
tDDWR
tWDE
tSADADC
6.5 + DT/16 + H
6.5 + DT/16 + H
WR High to WR, RD, DMAGx Low
Data Disable before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High2
–0.5 + DT /4
–0.5 + DT /4
W = (number of wait states specified in WAIT register) × tCK
.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOT ES
1ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC
2For MSx, SW, BMS, the falling edge is referenced.
.
3See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK
(OUT)
Figure 15. Mem ory Write—Bus Master
REV. A
–19–
ADI [ ADI ]
